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    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    21.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220302148A1

    公开(公告)日：2022-09-22

    申请号：US17205954

    申请日：2021-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Sidhartha Gupta ,  Kar Wui Thong ,  Harsh Narendrakumar Jain

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

    ELECTRONIC DEVICES WITH RECESSED CONDUCTIVE STRUCTURES AND RELATED METHODS AND SYSTEMS
    22.
    发明申请
    ELECTRONIC DEVICES WITH RECESSED CONDUCTIVE STRUCTURES AND RELATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220109002A1

    公开(公告)日：2022-04-07

    申请号：US17064092

    申请日：2020-10-06

    Applicant: Micron Technology, Inc

    Inventor： Sidhartha Gupta ,  Anilkumar Chandolu ,  S M Istiaque Hossain

    IPC: H01L27/11582 ,  H01L21/768 ,  G11C11/56

    Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

    Memory Array And Method Used In Forming A Memory Array
    23.
    发明申请
    Memory Array And Method Used In Forming A Memory Array 有权

    公开(公告)号：US20250024675A1

    公开(公告)日：2025-01-16

    申请号：US18904472

    申请日：2024-10-02

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma

    IPC: H10B41/27 ,  H01L23/538 ,  H10B43/27

    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

    Memory Circuitry Comprising Strings Of Memory Cells And Method Used In Forming Memory Circuitry Comprising Strings Of Memory Cells
    24.
    发明公开
    Memory Circuitry Comprising Strings Of Memory Cells And Method Used In Forming Memory Circuitry Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240355391A1

    公开(公告)日：2024-10-24

    申请号：US18618930

    申请日：2024-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Matthew J. King ,  Naveen Kaushik ,  Ravi Jadhav ,  Sidhartha Gupta

    IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming memory circuitry comprising strings of memory cells comprises forming vertically-alternating tiers of different composition first and second materials. The second material is insulative. The vertically-alternating tiers comprise a stack comprising laterally-spaced memory blocks. An inter-block column of openings is formed through the vertically-alternating tiers longitudinally-along and between immediately-laterally-adjacent of the memory blocks. An intra-block column of openings is formed through the vertically-alternating tiers longitudinally-along and within individual of the memory blocks. Individual of the intra-block columns of openings are entirely within one of the individual memory blocks. A first etchant is flowed into the inter-block columns of openings and into the intra-block columns of openings to etch the first material of the first-material tiers selectively relative to the second-material tiers to form a void-space tier vertically between immediately-vertically-adjacent of the second-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through the inter-block columns of openings and through the intra-block columns of openings into the void-space tiers. A second etchant is flowed into the inter-block columns of openings to remove the conductive material from being between the immediately-laterally-adjacent memory blocks in individual of the filled void-space tiers. Structures independent of method are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    29.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220238546A1

    公开(公告)日：2022-07-28

    申请号：US17158259

    申请日：2021-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma ,  Kyle A. Ritter

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

    Abstract: Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    30.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220157725A1

    公开(公告)日：2022-05-19

    申请号：US16952939

    申请日：2020-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta

    IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

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