公开(公告)号：US11640948B2

公开(公告)日：2023-05-02

申请号：US17198447

申请日：2021-03-11

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US11024629B2

公开(公告)日：2021-06-01

申请号：US16459002

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/108 ,  H01L21/308

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

公开(公告)号：US10388564B2

公开(公告)日：2019-08-20

申请号：US14993099

申请日：2016-01-12

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Wen-Chieh Wang ,  Sheng-Wei Yang

IPC: H01L21/768 ,  H01L21/764 ,  H01L29/06 ,  H01L27/108 ,  H01L27/11582 ,  H01L49/02 ,  H01L29/49

Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

公开(公告)号：US10128212B2

公开(公告)日：2018-11-13

申请号：US15676350

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L25/065

Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.

公开(公告)号：US10020310B2

公开(公告)日：2018-07-10

申请号：US15671471

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L21/336 ,  H01L27/108 ,  H01L27/11582

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

公开(公告)号：US20170373069A1

公开(公告)日：2017-12-28

申请号：US15700640

申请日：2017-09-11

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

公开(公告)号：US09786514B2

公开(公告)日：2017-10-10

申请号：US15296058

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2224/81

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side of the RDL interposer.

公开(公告)号：US20170213801A1

公开(公告)日：2017-07-27

申请号：US15003812

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/02 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/024 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

Abstract: A method for fabricating a package-on-package assembly is provided. A carrier with a passivation layer on the carrier is provided. A redistribution layer (RDL) is formed on the passivation layer. The RDL comprises at least one dielectric layer and at least one metal layer. The at least one metal layer comprises a plurality of first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer. The first bump pads are disposed within a chip mounting area, while the second pads are disposed within a peripheral area. At least one chip is then mounted on the first bump pads. The at least one chip is electrically connected to the RDL through first bumps on the first bump pads. A die package is then mounted on the second bump pads. The die package is electrically connected to the RDL through second bumps on the second bump pads.

公开(公告)号：US20210202417A1

公开(公告)日：2021-07-01

申请号：US17198447

申请日：2021-03-11

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US10950564B2

公开(公告)日：2021-03-16

申请号：US16414440

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.