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21.发明授权公开(公告)号：US11769561B2
公开(公告)日：2023-09-26
申请号：US17119509
申请日：2020-12-11
IPC分类号： G11C17/00 , G11C17/08 , G11C17/16 , G11C17/18 , G11C16/08 , G11C16/22 , G11C11/22 , G11C13/00 , G11C11/16
CPC分类号： G11C17/08 , G11C11/1653 , G11C11/1695 , G11C11/2253 , G11C11/2295 , G11C13/0004 , G11C13/0023 , G11C13/0059 , G11C16/08 , G11C16/22 , G11C17/165 , G11C17/18
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
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公开(公告)号：US20210358539A1
公开(公告)日：2021-11-18
申请号：US17387934
申请日：2021-07-28
IPC分类号： G11C11/406
摘要： Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
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23.发明授权公开(公告)号：US11062740B2
公开(公告)日：2021-07-13
申请号：US16834293
申请日：2020-03-30
摘要： A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.
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公开(公告)号：US10854274B1
公开(公告)日：2020-12-01
申请号：US16584746
申请日：2019-09-26
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4074
摘要： Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.
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25.发明授权公开(公告)号：US10692562B2
公开(公告)日：2020-06-23
申请号：US16734241
申请日：2020-01-03
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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26.发明申请公开(公告)号：US20190371392A1
公开(公告)日：2019-12-05
申请号：US16543477
申请日：2019-08-16
IPC分类号： G11C11/406
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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公开(公告)号：US20160372165A1
公开(公告)日：2016-12-22
申请号：US15251770
申请日：2016-08-30
CPC分类号： G11C7/065 , G11C5/06 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1036 , G11C7/22 , G11C8/10 , G11C11/4091 , G11C19/00 , G11C2207/002 , G11C2207/005
摘要： The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
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公开(公告)号：US09437256B2
公开(公告)日：2016-09-06
申请号：US14660219
申请日：2015-03-17
CPC分类号： G11C7/065 , G11C5/06 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1036 , G11C7/22 , G11C8/10 , G11C11/4091 , G11C19/00 , G11C2207/002 , G11C2207/005
摘要： The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
摘要翻译： 本公开包括与数据移位相关的装置和方法。 示例性设备包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移动阵列中的数据，而不经由阵列的输入/输出线传送数据。
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公开(公告)号：US11798610B2
公开(公告)日：2023-10-24
申请号：US17347957
申请日：2021-06-15
发明人： Timothy B. Cowles , Jiyun Li , Beau D. Barry , Matthew D. Jenkinson , Nathaniel J. Meier , Michael A. Shore , Adam J. Grenzebach , Dennis G. Montierth
IPC分类号： G11C11/401 , G11C11/406 , G11C11/408
CPC分类号： G11C11/40611 , G11C11/4085 , G11C11/4087 , G11C11/40618
摘要： An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
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公开(公告)号：US11341038B2
公开(公告)日：2022-05-24
申请号：US16808607
申请日：2020-03-04
IPC分类号： G06F12/02 , G06F3/06 , G11C16/10 , G06F11/10 , G11C29/52 , G11C16/08 , G11C16/26 , G11C16/34 , G11C7/24 , G11C7/06
摘要： The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.
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