-
公开(公告)号：US20190252015A1
公开(公告)日：2019-08-15
申请号：US15895671
申请日：2018-02-13
Applicant: Micron Technology, Inc.
Inventor： Gurtej S. Sandhu , Wayne I. Kinney
IPC: G11C11/16
Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.
-
22.发明申请公开(公告)号：US20180331113A1
公开(公告)日：2018-11-15
申请号：US15590863
申请日：2017-05-09
Applicant: Micron Technology, Inc.
Inventor： Albert Liao , Wayne I. Kinney , Yi Fang Lee , Manzar Siddik
IPC: H01L27/11507 , H01L27/11509 , H01L49/02 , G11C11/22
CPC classification number: H01L27/11507 , G11C11/221 , G11C11/2297 , H01L27/11509 , H01L28/55
Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
-
公开(公告)号：US09871044B2
公开(公告)日：2018-01-16
申请号：US14934659
申请日：2015-11-06
Applicant: Micron Technology, Inc.
Inventor： Sumeet C. Pandey , Gurtej S. Sandhu , Wayne I. Kinney , Karl W. Holtzclaw
IPC: H01L27/108 , G11C11/407 , G11C11/404 , H01L49/02
CPC classification number: H01L27/10808 , G11C11/404 , G11C11/407 , H01L28/65
Abstract: Volatile memory cells including dielectric materials exhibiting a nonlinear capacitance as a function of voltage. The volatile memory cells comprise a source region and a drain region within a substrate and a capacitor coupled to one of the source region and the drain region. The capacitor includes a charge storage material disposed between a pair of electrodes. The charge storage material has a crystal structure comprising an oxide of zirconium, hafnium, and bismuth, and is configured and formulated to transition from a first phase to a second phase exhibiting a higher capacitance than the first phase responsive to application of an electrical field. A digit line is electrically coupled to at least one electrode of the pair of electrodes and one of the source region and the drain region. Semiconductor devices and systems including the volatile memory cells and related methods of operating the volatile memory cells are also described.
-
公开(公告)号：US09356229B2
公开(公告)日：2016-05-31
申请号：US14728268
申请日：2015-06-02
Applicant: Micron Technology, Inc.
Inventor： Wayne I. Kinney , Witold Kula , Stephen J. Kramer
CPC classification number: H01L27/222 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01F10/3218 , H01F10/329 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely-directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication.
Abstract translation: 公开了存储单元。 存储单元内的磁性区域包括磁性子区域和耦合器子区域的交替结构。 耦合器子区域的耦合器材料反铁磁耦合相邻磁性子区域并且影响或促进相邻磁性子区域呈现的垂直磁性取向。 通过耦合器子区彼此间隔开的相邻的磁子区域表现出相反方向的磁取向。 磁性和耦合器子区域可以各自具有被调整以在紧凑结构中形成磁性区域的厚度。 可以减少或消除在切换存储单元中的自由区域时从磁性区域发射的磁偶极子场之间的干扰。 还公开了半导体器件结构，自旋扭矩传递磁随机存取存储器（STT-MRAM）系统和制造方法。
-
公开(公告)号：US12048167B2
公开(公告)日：2024-07-23
申请号：US17806674
申请日：2022-06-13
Applicant: Micron Technology, Inc.
Inventor： Witold Kula , Wayne I. Kinney , Gurtej S. Sandhu
CPC classification number: H10B61/00 , G11C11/161 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , H10B61/22
Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.
-
Patent Agency Ranking
26.发明授权公开(公告)号：US11515331B2
公开(公告)日：2022-11-29
申请号：US17003813
申请日：2020-08-26
Applicant: Micron Technology, Inc.
Inventor： Wayne I. Kinney
IPC: H01L27/115 , H01L27/11597 , H01L27/11592 , H01L23/528 , H01L27/1159 , G11C11/22 , H01L29/78 , H01L29/10 , H01L29/08 , H01L29/66 , H01L29/423 , H01L27/1157 , H01L27/11514 , H01L27/11582
Abstract: Some embodiments include an integrated assembly having a semiconductor structure extending from a first wiring to a second wiring. A ferroelectric transistor includes a first transistor gate adjacent a first region of the semiconductor structure. A first non-ferroelectric transistor includes a second transistor gate adjacent a second region of the semiconductor structure. The second region of the semiconductor structure is between the first region of the semiconductor structure and the first wiring. A second non-ferroelectric transistor includes a third transistor gate adjacent a third region of the semiconductor structure. The third region of the semiconductor structure is between the first region of the semiconductor structure and the second wiring.
-
公开(公告)号：US10726899B2
公开(公告)日：2020-07-28
申请号：US16201478
申请日：2018-11-27
Applicant: Micron Technology, Inc.
Inventor： Albert Liao , Wayne I. Kinney , Yi Fang Lee , Manzar Siddik
IPC: G11C11/22 , H01L27/11507 , H01L49/02 , H01L27/11509
Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
-
公开(公告)号：US10707298B2
公开(公告)日：2020-07-07
申请号：US16121966
申请日：2018-09-05
Applicant: Micron Technology, Inc.
Inventor： Michael Mutch , Manuj Nahar , Wayne I. Kinney
IPC: H01L21/20 , H01L29/04 , H01L21/02 , H01L29/161 , H01L21/324 , H01L29/786 , H01L27/105
Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.
-
29.发明申请公开(公告)号：US20190096897A1
公开(公告)日：2019-03-28
申请号：US16201478
申请日：2018-11-27
Applicant: Micron Technology, Inc.
Inventor： Albert Liao , Wayne I. Kinney , Yi Fang Lee , Manzar Siddik
IPC: H01L27/11507 , H01L27/11509 , G11C11/22 , H01L49/02
Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
-
公开(公告)号：US20180145112A1
公开(公告)日：2018-05-24
申请号：US15877064
申请日：2018-01-22
Applicant: Micron Technology, Inc.
Inventor： Witold Kula , Wayne I. Kinney , Gurtej S. Sandhu
CPC classification number: H01L27/222 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
43
records
(took 0.02 seconds)
