公开(公告)号：US11615830B2

公开(公告)日：2023-03-28

申请号：US17339047

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Seungjune Jeon ,  Zhengang Chen ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C11/00 ,  G11C11/406 ,  G11C11/16

Abstract: A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.

公开(公告)号：US11520491B2

公开(公告)日：2022-12-06

申请号：US17228086

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

公开(公告)号：US11455194B2

公开(公告)日：2022-09-27

申请号：US16510426

申请日：2019-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tingjun Xie ,  Zhengang Chen ,  Zhenlei Shen

IPC: G06F9/46 ,  G06F9/50 ,  G11C11/4074 ,  G06F12/06

Abstract: An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.

公开(公告)号：US11438012B2

公开(公告)日：2022-09-06

申请号：US16205075

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Wei Wu ,  Zhenlei Shen ,  Zhengang Chen

IPC: H03M13/15 ,  G06F11/10

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

公开(公告)号：US20220261345A1

公开(公告)日：2022-08-18

申请号：US17736824

申请日：2022-05-04

Applicant: Micron Technology Inc.

Inventor： Mikai Chen ,  Zhengang Chen ,  Charles See Yeung Kwong

IPC: G06F12/06 ,  G06F12/02

Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.

公开(公告)号：US20210311868A1

公开(公告)日：2021-10-07

申请号：US16837315

申请日：2020-04-01

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G11C11/56 ,  H04L9/06 ,  H04L9/08

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US11037637B2

公开(公告)日：2021-06-15

申请号：US16215267

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44 ,  G11C29/04

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).

公开(公告)号：US11023171B2

公开(公告)日：2021-06-01

申请号：US16514820

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.

公开(公告)号：US20210090683A1

公开(公告)日：2021-03-25

申请号：US17247254

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/30

Abstract: A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range.

公开(公告)号：US20210042224A1

公开(公告)日：2021-02-11

申请号：US16531305

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhengang Chen ,  Charles See Yeung Kwong

IPC: G06F12/06 ,  G06F12/02

Abstract: Data can be received to be stored at a memory component. A first location of a first layer of the memory component to store a first portion of the data can be determined. A second location of a second layer of the memory component to store a second portion of the data can be determined, where the second layer is different from the first layer. The first portion of the data can be stored at the first layer of the memory component and the second portion of the data can be stored at the second layer of the memory component.