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    ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER
    21.
    发明申请
    ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER 有权
    不对称双向硅控制整流器

    公开(公告)号：US20090032837A1

    公开(公告)日：2009-02-05

    申请号：US12113410

    申请日：2008-05-01

    Applicant: Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

    Inventor： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

    IPC: H01L29/747

    CPC classification number: H01L29/747 ,  H01L27/0262 ,  H01L29/87

    Abstract: The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

    Abstract translation: 本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到 硅控整流器。

    ESD protection circuit with active triggering
    22.
    发明申请
    ESD protection circuit with active triggering 有权
    具有主动触发的ESD保护电路

    公开(公告)号：US20090021872A1

    公开(公告)日：2009-01-22

    申请号：US11826634

    申请日：2007-07-17

    Applicant: Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

    Inventor： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

    IPC: H02H3/22

    CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

    Abstract translation: 提供ESD保护电路。 电路包括放电元件，二极管和ESD检测电路。 放电元件耦合在IC的输入/输出焊盘和第一电源线之间。 所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。 电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。 触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。 触发元件的输入耦合到电容器和电阻器之间的节点。

    Charge-device model electrostatic discharge protection using active device for CMOS circuits
    23.
    发明授权
    Charge-device model electrostatic discharge protection using active device for CMOS circuits 有权
    使用有源器件的CMOS电路的充电器件型静电放电保护

    公开(公告)号：US07253453B2

    公开(公告)日：2007-08-07

    申请号：US10442261

    申请日：2003-05-21

    Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

    Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

    IPC: H01L21/336

    CPC classification number: H01L27/0266

    Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.

    Abstract translation: 一种用于提供静电放电保护的集成电路，其包括接触焊盘，包括具有衬底的晶体管的CMOS器件和用于提供耦合在所述接触焊盘和所述CMOS器件之间的静电放电保护的CDM钳位，所述CDM夹具包括至少一个 有源器件，其中CDM钳位将积聚在晶体管的衬底中的静电电荷传导到接触焊盘，并且其中CMOS器件耦合在高压线和低电压线之间。

    Electrostatic discharge protection circuit with active device
    24.
    发明授权
    Electrostatic discharge protection circuit with active device 有权
    带有源器件的静电放电保护电路

    公开(公告)号：US07092227B2

    公开(公告)日：2006-08-15

    申请号：US10230287

    申请日：2002-08-29

    Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

    Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

    IPC: H02H9/00 ,  H02H3/22 ,  H01L27/01

    CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrostatic discharge protection circuit includes a first terminal, a second terminal, an electrostatic discharge device coupled between the first and second terminals, and an active device coupled to the electrostatic discharge device and controlling an electrostatic current through the electrostatic discharge device. The electrostatic discharge device includes at least one of an SCR, an FOD, an active device, a BJT, and an MOS device.

    Abstract translation: 静电放电保护电路包括第一端子，第二端子，耦合在第一和第二端子之间的静电放电装置，以及耦合到静电放电装置的有源装置，并且控制通过静电放电装置的静电电流。 静电放电装置包括SCR，FOD，有源器件，BJT和MOS器件中的至少一个。

    Electrostatic discharge protection device and method using depletion switch
    25.
    发明申请
    Electrostatic discharge protection device and method using depletion switch 审中-公开
    静电放电保护装置及使用耗尽开关的方法

    公开(公告)号：US20050219780A1

    公开(公告)日：2005-10-06

    申请号：US11137173

    申请日：2005-05-25

    Applicant: Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

    Inventor： Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

    IPC: H01L23/58 ,  H01L27/02 ,  H02H9/00

    CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit device for electrostatic discharge protection that includes a semiconductor substrate, a lightly doped region of a first dopant type formed in the substrate, a first diffusion region of the first dopant type formed at least partially in the lightly doped region, a second diffusion region of the first dopant type formed at least partially in the lightly doped region and spaced apart from the first diffusion region, a resistive path defined by the lightly doped region, the first and the second diffusion regions, and a third diffusion region of a second dopant type formed in the lightly doped region, and disposed between and spaced apart from the first and the second diffusion regions, wherein the third diffusion region keeps the resistive path at a low resistive state until a normal operation period occurs.

    Abstract translation: 一种用于静电放电保护的集成电路装置，包括半导体衬底，形成在衬底中的第一掺杂剂类型的轻掺杂区域，至少部分形成在轻掺杂区域中的第一掺杂剂类型的第一扩散区，第二扩散 所述第一掺杂剂类型的区域至少部分地形成在所述轻掺杂区域中并且与所述第一扩散区间隔开;由所述轻掺杂区域，所述第一和第二扩散区域以及第二扩散区域的第三扩散区域限定的电阻路径 掺杂剂类型形成在轻掺杂区域中，并且设置在第一和第二扩散区域之间并与第一和第二扩散区域间隔开，其中第三扩散区域将电阻路径保持在低电阻状态直到发生正常操作周期。

    Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process
    29.
    发明授权
    Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process 有权
    使用闩锁植入的结构和制造方法，以提高CMOS制造工艺中的闭锁抗扰度

    公开(公告)号：US06465283B1

    公开(公告)日：2002-10-15

    申请号：US09654810

    申请日：2000-09-05

    Applicant: Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

    Inventor： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

    IPC: H01L21332

    CPC classification number: H01L21/823814 ,  H01L21/823878 ,  H01L27/0921

    Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

    Abstract translation: 使用闭锁注入来提高CMOS电路中的闭锁抑制的结构和制造方法。 通过在寄生SCR的阴极和阳极上执行离子注入工艺来提高寄生SCR导通路径的阻抗，这可能引起闩锁现象。 因此，寄生SCR因此不容易以更高的抗噪声进行。 因此，可以提高闩锁抗扰度。 此外，可以进行离子注入工艺以实现防止闩锁效应的目的，而不消耗更多的布局面积，从而大大增强了电路设计的灵活性。

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