利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

75 条记录 (耗时 0.027 秒)

    Semiconductor device and method of manufacturing the same
    21.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08330196B2

    公开(公告)日：2012-12-11

    申请号：US13419947

    申请日：2012-03-14

    申请人： Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66984 ,  H01L21/823814 ,  H01L21/84 ,  H01L21/845 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/49 ,  H01L29/66075

    摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

    摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。

    Nonvolatile memory circuit using spin MOS transistors
    23.
    发明授权
    Nonvolatile memory circuit using spin MOS transistors 有权
    使用自旋MOS晶体管的非易失性存储电路

    公开(公告)号：US08154916B2

    公开(公告)日：2012-04-10

    申请号：US12889881

    申请日：2010-09-24

    申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/14

    CPC分类号： G11C14/0081

    摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

    摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

    LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY
    24.
    发明申请
    LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
    查看表电路和现场可编程门阵列

    公开(公告)号：US20120074984A1

    公开(公告)日：2012-03-29

    申请号：US13238020

    申请日：2011-09-21

    申请人： Hideyuki SUGIYAMA ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki SUGIYAMA ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： H03K19/177 ,  H03K5/00

    CPC分类号： H03K19/177

    摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.

    摘要翻译： 根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

    Semiconductor integrated circuit
    25.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08111087B2

    公开(公告)日：2012-02-07

    申请号：US12408953

    申请日：2009-03-23

    申请人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    发明人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    IPC分类号： H03K19/094

    CPC分类号： G11C14/0081 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/02 ,  G11C2213/31 ,  G11C2213/32 ,  H03K19/0944 ,  H03K19/18

    摘要： A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

    摘要翻译： 半导体集成电路包括包括磁性隧道结和磁半导体结之一的n沟道自旋FET，所述n沟道自旋FET包括用于接收输入信号的栅极端子，用于接收第一电源的源极端子 电位和连接到输出端的漏极端子，包括用于接收时钟信号的栅极端子的p沟道FET，用于接收第二电源电位的源极端子和连接到输出端子的漏极端子，后续 连接到输出端子的电路，以及控制电路，其导通p沟道FET以开始对输出端子充电，然后关闭p沟道FET以结束充电，并将输入信号提供给 n沟道自旋FET。

    Spin MOSFET and reconfigurable logic circuit
    30.
    发明授权
    Spin MOSFET and reconfigurable logic circuit 有权
    旋转MOSFET和可重构逻辑电路

    公开(公告)号：US08637946B2

    公开(公告)日：2014-01-28

    申请号：US13228852

    申请日：2011-09-09

    申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    IPC分类号： H01L29/82

    CPC分类号： H01L43/02 ,  B01D53/1493 ,  B01D53/62 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L28/00 ,  H01L29/0843 ,  H01L29/0895 ,  H01L29/66984 ,  H01L43/10

    摘要： A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

    摘要翻译： 自旋MOSFET包括：设置在半导体衬底上并具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在第二铁磁层上的第一隧道势垒; 设置在第一隧道屏障上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。