公开(公告)号：US08691710B2

公开(公告)日：2014-04-08

申请号：US13362077

申请日：2012-01-31

申请人： Wade Hampton Bailey, III ,  Sergei Vladimirovich Ivanov ,  Xinjian Lei ,  Moo-Sung Kim

发明人： Wade Hampton Bailey, III ,  Sergei Vladimirovich Ivanov ,  Xinjian Lei ,  Moo-Sung Kim

IPC分类号： C07D207/46 ,  H01L21/70

CPC分类号： C23C16/45553 ,  C07F7/003 ,  C23C16/405

摘要： Metal-containing complexes with general formula (1) (R1nPyr)(R2nPyr)ML1L2; or (2) [(R8XR9)(R1nPyr)(R2nPyr)]ML1L2 are disclosed; wherein M is a Group IV metal, Pyr is pyrrolyl ligand, n=1, 2 and 3, L1 and L2 are independently selected from alkoxide, amide or alkyl, L1 and L2 can be linked together, R1 and R2 can be same or different organic groups substituted at 2,3,4-positions of the pyrrole ring and are selected from the group consisting of linear and branched C1-6 alkyls, R8 and R9 are independently selected from the linear or branched chain alkylene group having 2-6 carbon atoms, and X is CH2 or oxygen. Methods of using the metal complexes as precursors to deposit metal or metal oxide films used for various devices in semi-conductor industries are also discussed.

摘要翻译： 含有通式（1）（R1nPyr）（R2nPyr）的金属络合物ML1L2; 或（2）[（R8XR9）（R1nPyr）（R2nPyr）] ML1L2; 其中M是第IV族金属，Pyr是吡咯基配体，n = 1,2和3，L1和L2独立地选自烷氧基，酰胺或烷基，L1和L2可以连接在一起，R1和R2可以相同或不同 在吡咯环的2,3,4位被取代的有机基团，并且选自直链和支链C 1-6烷基，R 8和R 9独立地选自具有2-6个碳原子的直链或支链亚烷基 原子，X是CH 2或氧。 还讨论了使用金属络合物作为前体沉积用于半导体工业中各种器件的金属或金属氧化物膜的方法。

公开(公告)号：US08202808B2

公开(公告)日：2012-06-19

申请号：US12793611

申请日：2010-06-03

申请人： Laura M. Matz ,  Xiangxin Rui ,  Xinjian Lei ,  Sunil Shanker ,  Moo-Sung Kim ,  Iain Buchanan

发明人： Laura M. Matz ,  Xiangxin Rui ,  Xinjian Lei ,  Sunil Shanker ,  Moo-Sung Kim ,  Iain Buchanan

IPC分类号： H01L21/285

CPC分类号： C23C16/45531 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/3142 ,  H01L21/31691 ,  H01L28/56

摘要： Embodiments of the current invention include methods of forming a strontium titanate (SrTiO3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO2 and SrO unit films is less than approximately 5 angstroms. The TiO2 and SrO units films are then annealed to form a strontium titanate layer.

摘要翻译： 本发明的实施方案包括使用原子层沉积（ALD）形成钛酸锶（SrTiO 3）膜的方法。 更具体地说，该方法包括使用ALD形成多个氧化钛（TiO 2）单元膜并使用ALD形成多个氧化锶（SrO）单元膜。 TiO 2和SrO单元膜的组合厚度小于约5埃。 然后将TiO 2和SrO单元膜退火以形成钛酸锶层。

公开(公告)号：US08092870B2

公开(公告)日：2012-01-10

申请号：US12410529

申请日：2009-03-25

申请人： Moo-Sung Kim ,  Xinjian Lei ,  Daniel P. Spence ,  Sang-Hyun Yang

发明人： Moo-Sung Kim ,  Xinjian Lei ,  Daniel P. Spence ,  Sang-Hyun Yang

IPC分类号： H05H1/24 ,  C23C16/00

CPC分类号： C23C16/409 ,  C23C16/45553

摘要： A cyclic deposition process to make a metal oxide film on a substrate, which comprises the steps: introducing a metal ketoiminate into a deposition chamber and depositing the metal ketoiminate on a heated substrate; purging the deposition chamber to remove unreacted metal ketominate and any byproduct; introducing an oxygen-containing source to the heated substrate; purging the deposition chamber to remove any unreacted chemical and byproduct; and, repeating the cyclic deposition process until a desired thickness of film is established.

摘要翻译： 一种在衬底上形成金属氧化物膜的循环沉积工艺，其包括以下步骤：将金属酮亚胺引入淀积室并将金属酮嘧啶沉积在加热的衬底上; 清除沉积室以除去未反应的金属酮基甲酸酯和任何副产物; 将含氧源引入加热的基底; 清除沉积室以除去任何未反应的化学和副产物; 并重复循环沉积过程，直到建立所需的膜厚。

公开(公告)号：US08085589B2

公开(公告)日：2011-12-27

申请号：US12881321

申请日：2010-09-14

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3427

摘要： A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

摘要翻译： 一种对闪存进行编程的方法包括通过向所选择的字线施加第一电压并将第二电压施加到未选择的字线来连接到所选字线的编程存储单元，所述第二电压低于所述第一电压， 在对连接到所选字线的存储单元进行编程之后，所选字线的第一电压为第三电压，第三电压低于第一电压，并且恢复所选字线和未选字线的第四电压 ，第四电压低于第二和第三电压。

公开(公告)号：US07697327B2

公开(公告)日：2010-04-13

申请号：US12145531

申请日：2008-06-25

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/00

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

摘要翻译： 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US07688631B2

公开(公告)日：2010-03-30

申请号：US12171701

申请日：2008-07-11

申请人： Moo-Sung Kim ,  Sung-Soo Lee

发明人： Moo-Sung Kim ,  Sung-Soo Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12

摘要： Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.

摘要翻译： 提供了一种对闪速存储器件进行编程的方法，包括根据表示为多级存储器单元的阈值电压分布的数据状态来设置编程电压的增量。 增量步进脉冲编程（ISPP）时钟信号对应于环路时钟信号，并且编程电压的增量是响应程序通过/失败信息产生的。 响应于环路时钟信号，通过执行计数操作直到达到编程电压的增量来产生默认电平使能信号。 响应于ISPP时钟信号，通过执行计数操作直到达到编程电压的增量来产生附加电平使能信号。 响应于默认电平使能信号，程序电压增加1个增量。 响应于附加电平使能信号，编程电压增加2个增量。

公开(公告)号：US20090016104A1

公开(公告)日：2009-01-15

申请号：US12216591

申请日：2008-07-08

申请人： Moo-Sung Kim

发明人： Moo-Sung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

摘要： A programming method of a multi-bit flash memory device includes programming multi-bit data into selected memory cells through pluralities of programming loops. In each programming loop, an increment of a programming voltage applied to the selected memory cells is varied in accordance with a result of program-verification for each data state of the multi-bit data and reading-verification for a data state is skipped when the program-verification indicates that data state has passed.

摘要翻译： 多位闪存器件的编程方法包括通过多个编程环将多位数据编程到所选存储单元中。 在每个编程环路中，根据多位数据的每个数据状态的程序验证结果，对施加到所选存储单元的编程电压的增量进行变化，并且当数据状态的读取验证被跳过时 程序验证表明数据状态已经过去。

公开(公告)号：US20080318443A1

公开(公告)日：2008-12-25

申请号：US12157631

申请日：2008-06-12

申请人： Min-Kyung Kim ,  Yang-Suk Han ,  Moo-Sung Kim ,  Sang-Hyun Yang ,  Xinjian Lei

发明人： Min-Kyung Kim ,  Yang-Suk Han ,  Moo-Sung Kim ,  Sang-Hyun Yang ,  Xinjian Lei

IPC分类号： H01L21/285 ,  C23C16/34

CPC分类号： C23C16/34 ,  C23C16/45531 ,  C23C16/45542 ,  C23C16/45553

摘要： The present invention relates to a method for forming a metal silicon nitride film according to a cyclic film deposition under plasma atmosphere with a metal amide, a silicon precursor, and a nitrogen source gas as precursors. The deposition method for forming a metal silicon nitride film on a substrate comprises steps of: pulsing a metal amide precursor; purging away the unreacted metal amide; introducing nitrogen source gas into reaction chamber under plasma atmosphere; purging away the unreacted nitrogen source gas; pulsing a silicon precursor; purging away the unreacted silicon precursor; introducing nitrogen source gas into reaction chamber under plasma atmosphere; and purging away the unreacted nitrogen source gas.

摘要翻译： 本发明涉及一种在金属酰胺，硅前体和氮源气体作为前体的等离子体气氛下，根据循环膜沉积形成金属氮化硅膜的方法。 用于在衬底上形成金属氮化硅膜的沉积方法包括以下步骤：脉冲金属酰胺前体; 清除未反应的金属酰胺; 在等离子体气氛下将氮源气体引入反应室; 清除未反应的氮源气体; 脉冲硅前体; 清除未反应的硅前体; 在等离子体气氛下将氮源气体引入反应室; 并清除未反应的氮源气体。

公开(公告)号：US07345923B2

公开(公告)日：2008-03-18

申请号：US11321282

申请日：2005-12-29

申请人： Moo-Sung Kim

发明人： Moo-Sung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628

摘要： A wordline voltage generation circuit generates an incremental step pulse voltage and includes a first circuit unit connected to a program voltage, a second circuit unit connected between the first circuit unit and a divided voltage and controlled by a program step code, and a third circuit unit connected between the divided voltage and a ground voltage. An increment of the program voltage is set according to a resistance of the third circuit unit without a change in the program step code. The first circuit unit is symmetrical in structure to the third circuit unit, and an increment of the program voltage is set by controlling a relationship between a resistance of the first circuit unit and a resistance of the third circuit unit, while maintaining a start program voltage or a target program voltage at a fixed value without a change in the program step code.

摘要翻译： 字线电压产生电路产生增量的步进脉冲电压，并且包括连接到编程电压的第一电路单元，连接在第一电路单元和分压之间并由程序步进代码控制的第二电路单元，以及第三电路单元 连接在分压和接地电压之间。 编程电压的增量根据第三电路单元的电阻而设定，而不改变程序步骤代码。 第一电路单元在结构上与第三电路单元对称，并且通过控制第一电路单元的电阻和第三电路单元的电阻之间的关系来设定编程电压的增量，同时保持启动编程电压 或目标程序电压为固定值，而不改变程序步骤代码。

公开(公告)号：US06855590B2

公开(公告)日：2005-02-15

申请号：US10650089

申请日：2003-08-28

申请人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

发明人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6659

摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

摘要翻译： 降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。 在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。 这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域 使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。