公开(公告)号：US07329940B2

公开(公告)日：2008-02-12

申请号：US11163882

申请日：2005-11-02

申请人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

IPC分类号： H01L27/082

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

公开(公告)号：US06635909B2

公开(公告)日：2003-10-21

申请号：US10101807

申请日：2002-03-19

申请人： William F. Clark ,  David M. Fried ,  Louis D. Lanzerotti ,  Edward J. Nowak

发明人： William F. Clark ,  David M. Fried ,  Louis D. Lanzerotti ,  Edward J. Nowak

IPC分类号： H01L310328

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

摘要： A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

公开(公告)号：US06426265B1

公开(公告)日：2002-07-30

申请号：US09774126

申请日：2001-01-30

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：US08030167B2

公开(公告)日：2011-10-04

申请号：US11839106

申请日：2007-08-15

申请人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

IPC分类号： H01L21/33 ,  H01L27/102 ,  H01L29/73

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US08022496B2

公开(公告)日：2011-09-20

申请号：US11873696

申请日：2007-10-17

申请人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

IPC分类号： H01L29/47

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

公开(公告)号：US20090057815A1

公开(公告)日：2009-03-05

申请号：US12263646

申请日：2008-11-03

申请人： Louis D. Lanzerotti ,  Stephen A. St. Onge

发明人： Louis D. Lanzerotti ,  Stephen A. St. Onge

IPC分类号： H01L23/58

CPC分类号： H01L21/823481 ,  H01L21/76237 ,  H01L29/78

摘要： Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.

摘要翻译： 公开了制造半导体结构的方法，其包括深沟槽隔离，其中在深沟槽蚀刻和在衬底上形成晶体管器件（FEOL处理）之前在衬底中以嵌入杂质区的形式形成沟道阻挡。 以这种方式，FEOL处理热循环可以激活杂质区域。 然后在FEOL处理后形成深沟槽隔离。 该方法实现了在FEOL处理之后形成深沟槽隔离的成本降低，并且允许在设备之间共享收集器级别的实践继续进行。 本发明还包括如此形成的半导体结构。

公开(公告)号：US07491614B2

公开(公告)日：2009-02-17

申请号：US10905627

申请日：2005-01-13

申请人： Louis D. Lanzerotti ,  Stephen A. St Onge

发明人： Louis D. Lanzerotti ,  Stephen A. St Onge

IPC分类号： H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76237 ,  H01L29/78

摘要： Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue.

摘要翻译： 公开了制造半导体结构的方法，其包括深沟槽隔离，其中在深沟槽蚀刻和在衬底上形成晶体管器件（FEOL处理）之前在衬底中以嵌入杂质区的形式形成沟道阻挡。 以这种方式，FEOL处理热循环可以激活杂质区域。 然后在FEOL处理后形成深沟槽隔离。 该方法实现了在FEOL处理之后形成深沟槽隔离的成本降低，并且允许在设备之间共享收集器级别的实践继续进行。

公开(公告)号：US20080124881A1

公开(公告)日：2008-05-29

申请号：US11562735

申请日：2006-11-22

申请人： Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US07374988B2

公开(公告)日：2008-05-20

申请号：US11378786

申请日：2006-03-17

申请人： Brent A. Anderson ,  Louis D. Lanzerotti ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Louis D. Lanzerotti ,  Edward J. Nowak

IPC分类号： H01L21/8238 ,  H01L21/31

CPC分类号： H01L29/0847 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 该场效应晶体管包括：形成在栅极电介质层的顶表面上的栅电极，单晶硅沟道区的顶表面上的栅介质层，顶表面上的单晶硅沟道区 包含Ge的层，在单晶硅衬底的顶表面上的Ge包括层，在单晶硅衬底的顶表面上的第一介电层和第二电介质层之间的Ge包括层。

公开(公告)号：US06900519B2

公开(公告)日：2005-05-31

申请号：US10865138

申请日：2004-06-10

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L27/082

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.