公开(公告)号：US06518154B1

公开(公告)日：2003-02-11

申请号：US09813310

申请日：2001-03-21

申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.

摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如， ，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。 本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

公开(公告)号：US06514858B1

公开(公告)日：2003-02-04

申请号：US09829202

申请日：2001-04-09

申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

IPC分类号： H01L214763

CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

公开(公告)号：US06444513B1

公开(公告)日：2002-09-03

申请号：US09810348

申请日：2001-03-19

申请人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

发明人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L218238

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  Y10S438/947 ,  Y10S438/949

摘要： A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

摘要翻译： 金属栅结构及其形成方法将金属杂质引入例如由TiN制成的第一金属层中。 这些杂质产生更大的蚀刻选择性的表面区域，其防止了在形成金属栅极结构期间在覆盖钨栅的蚀刻过程中TiN的过蚀刻。 防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。 提供铝或钽作为金属杂质提供了足够的蚀刻停止能力，并且不会不希望地影响TiN的功函数。

公开(公告)号：US06432805B1

公开(公告)日：2002-08-13

申请号：US09783620

申请日：2001-02-15

申请人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

发明人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

摘要翻译： 通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理 桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

公开(公告)号：US06368950B1

公开(公告)日：2002-04-09

申请号：US09734186

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28097

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

公开(公告)号：US06342414B1

公开(公告)日：2002-01-29

申请号：US09734189

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L218238

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低 温度金属硅化物门。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06329277B1

公开(公告)日：2001-12-11

申请号：US09417839

申请日：1999-10-14

申请人： Bill Yowjuang Liu ,  Paul R. Besser

发明人： Bill Yowjuang Liu ,  Paul R. Besser

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.

摘要翻译： 形成硅化物区域的半导体布置和方法包括在硅衬底上共形沉积还原材料层。 然后将难熔金属层共形沉积在还原材料层上。 然后进行退火以在硅衬底上形成难熔金属硅化物层。 金属硅化物层是硅化钴，还原材料层包括钽，镁，铝或钙中的至少一种。 还原材料减少硅衬底上的自然氧化物以形成硅化钴。

公开(公告)号：US06297107B1

公开(公告)日：2001-10-02

申请号：US09691228

申请日：2000-10-19

申请人： Eric Paton ,  Matthew S. Byunoski ,  Paul R. Besser ,  Paul L. King ,  Qi Xiang

发明人： Eric Paton ,  Matthew S. Byunoski ,  Paul R. Besser ,  Paul L. King ,  Qi Xiang

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.

摘要翻译： 通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。 实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

公开(公告)号：US06239494B1

公开(公告)日：2001-05-29

申请号：US09295357

申请日：1999-04-21

申请人： Paul R. Besser ,  Robin W. Cheung

发明人： Paul R. Besser ,  Robin W. Cheung

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85375 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.

摘要翻译： 通过在Cu互连和Al焊盘之间插入势垒层，实现了通过Al和Cu互扩散而减少的Cu互连通孔和Al焊盘的引线接合。 实施例包括在Cu互连和Al衬垫之间形成Ti，Ta，W的阻挡层，其合金或其氮化物。

公开(公告)号：US06204177B1

公开(公告)日：2001-03-20

申请号：US09185515

申请日：1998-11-04

申请人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

发明人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.

摘要翻译： 在具有减少的结漏电的半导体晶片中形成金属硅化物的方法在覆盖硅层的钴层内的钴晶界处引入合金。 在钴和合金元素的沉积期间，或者通过沉积后的中间退火，合金元素可以沉淀。 然后将钴层和硅层退火以形成金属硅化物区域。 通过在钴晶界析出合金，在第一快速热退火步骤期间，在晶界处的钴扩散被延迟。 鼓励扩散，并产生具有降低的界面粗糙度的更均匀的硅化物膜。 由于通过本发明的方法减小了界面粗糙度，所以结漏电减少。 这允许制造较浅的结，导致具有改进性能的器件。