公开(公告)号：US09984029B2

公开(公告)日：2018-05-29

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Stanley Seungchul Song ,  Xiangdong Chen ,  Raymond George Stephany ,  John Jianhong Zhu ,  Ohsang Kwon ,  Esin Terzioglu ,  Choh Fei Yeap

IPC: H01L23/528 ,  G06F13/40 ,  G06F13/42 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

公开(公告)号：US09972624B2

公开(公告)日：2018-05-15

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

公开(公告)号：US09887209B2

公开(公告)日：2018-02-06

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L21/44 ,  H01L27/118 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

公开(公告)号：US09786663B2

公开(公告)日：2017-10-10

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/482 ,  H01L27/02 ,  H03K17/16 ,  H03K17/687 ,  H01L23/522

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US09685940B2

公开(公告)日：2017-06-20

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/04 ,  H03K17/042 ,  H03K5/24 ,  H03K19/00 ,  H03K5/26

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

公开(公告)号：US09640480B2

公开(公告)日：2017-05-02

申请号：US14723357

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon

IPC: H01L23/528 ,  H01L27/088 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

公开(公告)号：US09190405B2

公开(公告)日：2015-11-17

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Satyanarayana Sahu ,  Divya Gangadharan ,  Chih-Iung Kao ,  Renukprasad Shreedhar Hiremath ,  Animesh Datta ,  Qi Ye

IPC: H01L27/00 ,  H01L27/088 ,  H01L29/06 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压时，栅极另一侧的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。

公开(公告)号：US20140226395A1

公开(公告)日：2014-08-14

申请号：US13767788

申请日：2013-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C2207/007

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。