公开(公告)号：US20190237542A1

公开(公告)日：2019-08-01

申请号：US15886611

申请日：2018-02-01

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L29/0696 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0642 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2027/11831 ,  H01L2027/11875

Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

公开(公告)号：US10236886B2

公开(公告)日：2019-03-19

申请号：US15393180

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H01L23/528 ,  H03K19/0948 ,  H01L27/118 ,  H01L23/522 ,  H01L27/02 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US10103626B1

公开(公告)日：2018-10-16

申请号：US15647326

申请日：2017-07-12

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Dorav Kumar ,  Ramaprasath Vilangudipitchai ,  Venugopal Boynapalli

IPC: H02M3/157 ,  H03K17/687 ,  H03K19/173 ,  H02M3/335

Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

公开(公告)号：US10038429B1

公开(公告)日：2018-07-31

申请号：US15683691

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Qi Ye ,  Manish Srivastava ,  Venugopal Boynapalli

IPC: H03K3/3562 ,  H03K3/013 ,  H03K3/356

CPC classification number: H03K3/35625 ,  H03K3/013 ,  H03K3/356139

Abstract: A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.

公开(公告)号：US09990984B1

公开(公告)日：2018-06-05

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav Kumar ,  Venkat Narayanan ,  Bilal Zafar ,  Seid Hadi Rasouli ,  Venugopal Boynapalli

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

公开(公告)号：US09979394B2

公开(公告)日：2018-05-22

申请号：US15044988

申请日：2016-02-16

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Animesh Datta ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli

IPC: H03K3/356 ,  H03K19/003 ,  H03K3/037 ,  H03K3/033 ,  H03K5/04

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

公开(公告)号：US09960231B2

公开(公告)日：2018-05-01

申请号：US15186326

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Satyanarayana Sahu ,  Venugopal Boynapalli

IPC: H01L21/82 ,  H01L29/06 ,  H01L23/535 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

公开(公告)号：US20160134286A1

公开(公告)日：2016-05-12

申请号：US14534967

申请日：2014-11-06

Applicant: QUALCOMM Incorporated

Inventor： Kevin Robert Bowles ,  Jose Gabriel Corona ,  Venugopal Boynapalli

IPC: H03K19/0185

CPC classification number: H03K19/018528 ,  H03K3/35613 ,  H03K17/002 ,  H03K17/005 ,  H03K19/018507

Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

Abstract translation: 本文描述了用于电平转换复用的系统和方法。 在一个实施例中，一种用于电平转换复用的方法包括：基于一个或多个选择信号选择多个输入中的一个，并且基于所述多个输入中所选择的一个输入的逻辑状态来下拉第一和第二节点中的一个 。 该方法还包括如果第二节点被拉下来则拉起第一节点，并且如果第一节点被拉下来则提起第二节点。

公开(公告)号：US20160004617A1

公开(公告)日：2016-01-07

申请号：US14323916

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Hari Madhava Rao ,  Joseph Weizhou Fang ,  Sami Khawam ,  Ioannis Nousias ,  Raju Macha ,  Ihab Abdelmuti ,  Venugopal Boynapalli

IPC: G06F11/22 ,  G06F13/40

CPC classification number: G06F11/2289 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/263 ,  G06F13/4022

Abstract: An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals.

Abstract translation: 提供了包括瓦片阵列的指令单元阵列。 每个瓦片包括用于在多个输入通道和多个相应的输出通道之间切换的一组输入/输出（I / O）端口。 此外，每个瓦片包括指令单元，该指令单元包括多个专用逻辑门，用于产生从瓦片的输入通道中的选定的输入通道输出的指令单元。 每个I / O端口被配置为从瓦片的指令单元输出和输入通道中选择用于瓦片的剩余I / O端口以形成I / O端口的输出通道。 为了在阵列的自动测试模式生成（ATPG）期间防止组合循环，本文公开的指令单元阵列被配置在测试模式中，使得每个瓦片的I / O端口的至少一个子集阻止其任何输出通道 被形成为组合信号。

公开(公告)号：US08860493B2

公开(公告)日：2014-10-14

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.