公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20150333008A1

公开(公告)日：2015-11-19

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/535 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract translation: 标准单元CMOS器件包括具有由栅极互连形成的栅极的金属氧化物半导体晶体管。 栅极互连沿第一方向延伸。 该器件还包括向晶体管提供功率的电源轨。 电源轨在与第一方向正交的第二方向上延伸。 该装置还包括在电源轨之间延伸的M1层互连。 M1层互连中的至少一个耦合到至少一个晶体管。 M1层互连平行于栅极互连并仅在第一方向上延伸。

公开(公告)号：US20150301973A1

公开(公告)日：2015-10-22

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Stanley Seungchul SONG ,  Xiangdong CHEN ,  Raymond George Stephany ,  John Jianhong ZHU ,  Ohsang KWON ,  Esin TERZIOGLU ,  Choh Fei YEAP

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。

公开(公告)号：US20150194339A1

公开(公告)日：2015-07-09

申请号：US14283162

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU ,  Xiangdong CHEN ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。

公开(公告)号：US20150144962A1

公开(公告)日：2015-05-28

申请号：US14322207

申请日：2014-07-02

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract translation: 互补翅片场效应晶体管（FinFET）包括具有p沟道鳍片的p型器件。 p沟道鳍可以包括相对于半导体衬底而晶格失配的第一材料。 第一种材料可能具有压缩应变。 FinFET器件还包括具有再通道鳍片的n型器件。 n沟道翅片可以包括具有相对于半导体衬底的晶格失配的拉伸应变的第二材料。 p型器件和n型器件配合形成互补FinFET器件。