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    Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods
    22.
    发明授权
    Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods 有权
    具有用于提供多模式向量处理的可编程数据路径配置的矢量处理引擎，以及相关的矢量处理器，系统和方法

    公开(公告)号：US09495154B2

    公开(公告)日：2016-11-15

    申请号：US13798641

    申请日：2013-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Raheel Khan

    IPC: G06F9/02 ,  G06F9/30 ,  G06F15/78 ,  G06F15/80 ,  G06F9/38

    CPC classification number: G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/8053 ,  Y02D10/12 ,  Y02D10/13

    Abstract: Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

    Abstract translation: 本文公开的实施例包括具有用于提供多模式向量处理的可编程数据路径配置的向量处理引擎（VPE）。 还公开了相关的矢量处理器，系统和方法。 VPE包括被配置为根据在矢量处理阶段中执行的矢量指令来处理矢量数据的矢量处理级。 每个矢量处理级包括矢量处理块，每个矢量处理块被配置为基于正在执行的矢量指令来处理矢量数据。 向量处理块能够基于数据路径配置为不同类型的向量指令提供不同的向量操作。 矢量处理块的数据路径可编程为可重新编程，以根据正在执行的特定向量指令不同地处理矢量数据。 以这种方式，可以为VPE提供可编程的数据路径配置，以根据正在执行的向量指令，基于数据路径配置来执行不同类型的功能。

    Vector processing engines having programmable data path configurations for providing multi-mode radix-2x butterfly vector processing circuits, and related vector processors, systems, and methods
    23.
    发明授权
    Vector processing engines having programmable data path configurations for providing multi-mode radix-2x butterfly vector processing circuits, and related vector processors, systems, and methods 有权
    具有可编程数据路径配置的向量处理引擎，用于提供多模式2×蝴蝶向量处理电路，以及相关的矢量处理器，系统和方法

    公开(公告)号：US09275014B2

    公开(公告)日：2016-03-01

    申请号：US13798599

    申请日：2013-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Raheel Khan

    IPC: G06F17/14 ,  G06F9/30 ,  G06F9/38 ,  G06F7/544 ,  G06F15/80

    CPC classification number: G06F17/142 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053 ,  G06F2207/382

    Abstract: Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2X butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2X butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.

    Abstract translation: 具有可编程数据路径配置的矢量处理引擎（VPE），用于提供多模Radix-2X蝴蝶向量处理电路。 还公开了相关的矢量处理器，系统和方法。 本文公开的VPE包括多个矢量处理级，每个矢量处理级具有矢量处理块，该矢量处理块具有用于执行基数-2X蝶矢量运算的可编程数据路径配置，以有效地执行快速傅里叶变换（FFT）矢量处理操作。 矢量处理块的数据路径配置可以被编程为提供不同类型的Radix-2X蝴蝶向量运算以及其他算术逻辑矢量运算。 因此，较少的VPE可以在向量处理器中提供期望的Radix-2X蝴蝶向量操作和其他类型的算术逻辑向量操作，从而节省向量处理器中的区域，同时仍然保留较少寄存器写入和更快矢量指令执行时间的向量处理优点 超标量处理引擎。

    TWIDDLE FACTOR GENERATION
    24.
    发明申请
    TWIDDLE FACTOR GENERATION 审中-公开

    公开(公告)号：US20150248374A1

    公开(公告)日：2015-09-03

    申请号：US14195442

    申请日：2014-03-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hung-Chih Lai ,  Samuel Sangmin Rhee ,  Dong Wook Seo ,  Raheel Khan

    IPC: G06F17/14

    CPC classification number: G06F17/142

    Abstract: Systems and methods for generating twiddle factors are described herein according to various embodiments of the present disclosure. In one embodiment, a method for twiddle factor generation comprises generating a first twiddle phase, wherein the first twiddle phase is from a set of radix-M1 twiddle phases, and M1 is an integer. The method also comprises converting the first twiddle phase into a second twiddle phase, wherein the second twiddle phase is from a set of radix-M2 twiddle phases, and M2 is an integer that is different from M1. The method further comprises generating a twiddle factor based on the second twiddle phase.

    Abstract translation: 根据本公开的各种实施例，本文描述了用于产生旋转因子的系统和方法。 在一个实施例中，一种用于旋转因子产生的方法包括产生第一旋转相位，其中第一旋转相位来自一组基数-M1旋转相位，M1是整数。 该方法还包括将第一旋转相位转换成第二旋转相位，其中第二旋转相位来自一组基数M2旋转相位，M2是不同于M1的整数。 该方法还包括基于第二旋转相位产生旋转因子。

    ON-THE-FLY CONVERSION DURING LOAD/STORE OPERATIONS IN A VECTOR PROCESSOR
    25.
    发明申请
    ON-THE-FLY CONVERSION DURING LOAD/STORE OPERATIONS IN A VECTOR PROCESSOR 审中-公开
    在矢量处理器中的载入/存储操作期间的转换

    公开(公告)号：US20150220339A1

    公开(公告)日：2015-08-06

    申请号：US14170193

    申请日：2014-01-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： Raheel Khan ,  Jun Ho Bahn ,  Vijay Bantval

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3875

    Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

    Abstract translation: 这里描述了用于在加载/存储操作期间对数据向量执行动态格式转换的系统和方法。 在一个实施例中，一种用于将数据向量从存储器加载到向量单元中的方法包括从存储器读取多个样本，其中多个样本被打包在存储器中。 该方法还包括拆包样本以获得多个未打包的样本，并行地对未打包的样本执行格式转换，以及将格式转换的样本的至少一部分发送到向量单元。

    SAMPLE PROCESS ORDERING FOR DFT OPERATIONS
    26.
    发明申请
    SAMPLE PROCESS ORDERING FOR DFT OPERATIONS 有权
    DFT操作的样品过程订购

    公开(公告)号：US20150199299A1

    公开(公告)日：2015-07-16

    申请号：US14157441

    申请日：2014-01-16

    Applicant: QUALCOMM Incorporated

    Inventor： Samuel Sangmin Rhee ,  Hung-Chih Lai ,  Dong Wook Seo ,  Raheel Khan

    IPC: G06F15/78

    CPC classification number: G06F15/78 ,  G06F9/30036 ,  G06F9/3885 ,  G06F17/14

    Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

    Abstract translation: 根据本公开的各种实施例在此描述用于以反向组顺序读取数据样本的系统和方法。 在一个实施例中，提供了一种用于在存储器中读取数据样本的方法，其中数据样本对应于向量操作的操作数，数据样本被分组成多个不同的组，并且不同的组被间隔开 存储器中的多个地址。 该方法包括以反向组顺序读取数据样本组，并且对于每个组，以正向顺序读取组中的数据样本。

    LOW-LATENCY LOW-UNCERTAINTY TIMER SYNCHRONIZATION MECHANISM ACROSS MULTIPLE DEVICES
    29.
    发明申请
    LOW-LATENCY LOW-UNCERTAINTY TIMER SYNCHRONIZATION MECHANISM ACROSS MULTIPLE DEVICES 审中-公开

    公开(公告)号：US20170223646A1

    公开(公告)日：2017-08-03

    申请号：US15251581

    申请日：2016-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

    IPC: H04W56/00 ,  H04W52/02 ,  H04L7/02

    CPC classification number: H04W56/001 ,  G06F13/4273 ,  H04L7/02 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/164 ,  Y02D70/26

    Abstract: Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

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