METHOD AND APPARATUS FOR MULTI-LEVEL DE-EMPHASIS
    21.
    发明申请
    METHOD AND APPARATUS FOR MULTI-LEVEL DE-EMPHASIS 有权
    用于多层次去除的方法和装置

    公开(公告)号:US20140176196A1

    公开(公告)日:2014-06-26

    申请号:US13725961

    申请日:2012-12-21

    IPC分类号: G05F3/02 H03K3/00

    CPC分类号: G05F3/262 H04L25/03847

    摘要: A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

    摘要翻译: 根据分配命令,分配电流被分成第一控制电流,第二控制电流和第三控制电流。 响应于第三控制电流产生第一控制电压。 产生第二控制电压作为第一控制电流的指示,并且产生第三控制电压作为第二控制电流的指示。 可选地,至少部分地基于第一控制电压,第二控制电压和第三控制电压来控制第一驱动器,第二驱动器和第三驱动器对输出的去加重贡献。

    ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP
    22.
    发明申请
    ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP 审中-公开
    用于测量半导体芯片动态电源噪声的片上传感器

    公开(公告)号:US20130285696A1

    公开(公告)日:2013-10-31

    申请号:US13928424

    申请日:2013-06-27

    IPC分类号: G01R31/317

    CPC分类号: G01R31/31721 G01R29/26

    摘要: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

    摘要翻译: 片上传感器测量半导体芯片上的动态电源噪声,如电压下降。 采用原位逻辑,对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器,加法器和/或其他功能逻辑。 原位逻辑执行一些操作,并且执行该操作所需的时间量(即,操作延迟)对电源上存在的噪声敏感。 因此,通过评估原位逻辑的操作延迟,可以测量电源上存在的噪声量。

    Power saving during a connection detection
    24.
    发明授权
    Power saving during a connection detection 有权
    连接检测期间省电

    公开(公告)号:US09465424B2

    公开(公告)日:2016-10-11

    申请号:US14167000

    申请日:2014-01-29

    IPC分类号: G06F1/26 G06F1/16 G06F1/32

    摘要: In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal.

    摘要翻译: 在特定实施例中,电子设备包括耦合到DC接口的直流(DC)电压源。 电子设备包括接收器感测电路,其被配置为经由连接器检测电子设备到宿设备的连接,而不消耗来自DC电压源的电力。 电子设备还包括耦合到热插拔检测(HPD)接口的控制器。 控制器被配置为从接收器感测电路接收检测信号,选择性地控制开关以基于检测信号启用和禁用DC电压源,在启用直流电压源之后检测HPD接口处的HPD信号,并禁用 接收机感测电路响应于检测到HPD信号。

    Serdes voltage-mode driver with skew correction
    25.
    发明授权
    Serdes voltage-mode driver with skew correction 有权
    带偏斜校正的Serdes电压模式驱动器

    公开(公告)号:US09264263B2

    公开(公告)日:2016-02-16

    申请号:US14257848

    申请日:2014-04-21

    摘要: A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.

    摘要翻译: 用于在通信链路上发送串行数据的驱动器电路组合电压模式和电流模式驱动器。 驱动电路使用电压模式驱动器作为主输出驱动器。 一个或多个辅助电流模式驱动器与电压模式驱动器并联连接,以通过向输出中注入电流来调整输出信号。 电压模式驱动器提供大部分输出驱动器。 因此,输出驱动器电路可以提供与电压模式驱动器相关联的功率效率益处。 电流模式驱动器可以提供例如预加重,电平调整,偏斜补偿和输出信号的其它修改。 因此,驱动器电路还可以提供与当前模式驱动器相关联的信号调节能力。

    High speed data testing without high speed bit clock
    26.
    发明授权
    High speed data testing without high speed bit clock 有权
    无高速位时钟的高速数据测试

    公开(公告)号:US09037437B2

    公开(公告)日:2015-05-19

    申请号:US14105213

    申请日:2013-12-13

    摘要: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式,其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样,以产生采样的第一高速数据路径,然后以低速基准时钟的速度进行测试。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    27.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 有权
    高速数据测试无高速位时钟

    公开(公告)号:US20140101507A1

    公开(公告)日:2014-04-10

    申请号:US14105213

    申请日:2013-12-13

    IPC分类号: G01R31/3177 G06F1/04

    摘要: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式,其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样,以产生采样的第一高速数据路径,然后以低速基准时钟的速度进行测试。