公开(公告)号：US20210041932A1

公开(公告)日：2021-02-11

申请号：US16947973

申请日：2020-08-26

Applicant: Rambus Inc.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US10831685B2

公开(公告)日：2020-11-10

申请号：US16546694

申请日：2019-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40 ,  G11C29/02

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US10402352B2

公开(公告)日：2019-09-03

申请号：US15333001

申请日：2016-10-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/00 ,  G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40 ,  G11C29/02

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20190171272A1

公开(公告)日：2019-06-06

申请号：US16193247

申请日：2018-11-16

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G06F1/3234 ,  G06F5/06 ,  G06F1/3287 ,  G11C11/4093

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US10067519B2

公开(公告)日：2018-09-04

申请号：US15626096

申请日：2017-06-17

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

IPC: G05F1/46 ,  G11C5/14

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

公开(公告)号：US09645631B2

公开(公告)日：2017-05-09

申请号：US15248364

申请日：2016-08-26

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G11C8/00 ,  G06F1/32 ,  G11C7/22 ,  G11C7/10 ,  G06F5/06

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US09432227B2

公开(公告)日：2016-08-30

申请号：US14575985

申请日：2014-12-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H03K5/159 ,  H04L25/03 ,  H03K5/24

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

公开(公告)号：US09417807B2

公开(公告)日：2016-08-16

申请号：US14820207

申请日：2015-08-06

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US20160041781A1

公开(公告)日：2016-02-11

申请号：US14820207

申请日：2015-08-06

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US20150333938A1

公开(公告)日：2015-11-19

申请号：US14720518

申请日：2015-05-22

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04B1/123 ,  H04L25/03063 ,  H04L25/03885

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract translation: 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。