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    SECURING ADDRESS INFORMATION IN A MEMORY CONTROLLER
    21.
    发明申请
    SECURING ADDRESS INFORMATION IN A MEMORY CONTROLLER 有权

    公开(公告)号：US20210064788A1

    公开(公告)日：2021-03-04

    申请号：US16997661

    申请日：2020-08-19

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Liji Gopalakrishnan ,  John Eric Linstadt ,  Steven C. Woo

    IPC: G06F21/75 ,  H04L9/00

    Abstract: Methods and systems for enabling secure memory transactions in a memory controller are disclosed. Responsive to determining that an incoming request is for a secure memory transaction, the incoming request is placed in a secure request container. The memory container then enters a state where re-ordering between requests for secure memory transactions placed in the secure request container and requests for non-secure memory transactions from other containers is prevented in a scheduling queue.

    EXTERNAL BLOCK TRANSFER IN A MEMORY SYSTEM
    22.
    发明申请
    EXTERNAL BLOCK TRANSFER IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200379926A1

    公开(公告)日：2020-12-03

    申请号：US15931405

    申请日：2020-05-13

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan

    IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/4093

    Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

    MEMORY WITH ALTERNATIVE COMMAND INTERFACES
    23.
    发明申请
    MEMORY WITH ALTERNATIVE COMMAND INTERFACES 审中-公开

    公开(公告)号：US20200004714A1

    公开(公告)日：2020-01-02

    申请号：US16520137

    申请日：2019-07-23

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

    IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16

    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

    Memory with Alternative Command Interfaces
    26.
    发明申请
    Memory with Alternative Command Interfaces 有权
    内存与替代命令接口

    公开(公告)号：US20160170924A1

    公开(公告)日：2016-06-16

    申请号：US15051282

    申请日：2016-02-23

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

    IPC: G06F13/40 ,  G06F13/16

    CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

    Abstract translation: 存储器件或模块在可选命令端口之间进行选择。 具有内存模块的内存系统包含这种内存设备，可支持点对点连接和不同数量模块的高效互连使用。 存储器件和模块可以是可编程数据宽度。 同一模块上的设备可以配置为选择不同的命令端口，以便于内存线程化。 模块同样可以配置为为同一目的选择不同的命令端口。

    POWER-MANAGEMENT FOR INTEGRATED CIRCUITS
    27.
    发明申请
    POWER-MANAGEMENT FOR INTEGRATED CIRCUITS 有权
    集成电路功率管理

    公开(公告)号：US20150348612A1

    公开(公告)日：2015-12-03

    申请号：US14799362

    申请日：2015-07-14

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

    IPC: G11C11/4076 ,  G11C11/4096

    CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

    Abstract translation: 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

    Memory system with multiple open rows per bank
    30.
    发明授权
    Memory system with multiple open rows per bank 有权

    公开(公告)号：US11842761B2

    公开(公告)日：2023-12-12

    申请号：US17390370

    申请日：2021-07-30

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  John Eric Linstadt ,  Liji Gopalakrishnan

    IPC: G06F12/00 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

    CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

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