-
21.发明授权Hazard prevention for data conflicts between level one data cache line allocates and snoop writes 有权第一级数据高速缓存行分配和窥探写入之间的数据冲突的危害预防公开(公告)号：US08856446B2
公开(公告)日：2014-10-07
申请号：US13247195
申请日：2011-09-28
申请人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
摘要翻译： 比较器将FIFO堆栈的最终条目中的DMA写入的地址与监视器存储器中的所有挂起的读取地址进行比较。 如果没有匹配，则允许DMA访问继续。 如果DMA写入到具有待处理读取的高速缓存行，则DMA写入访问与FIFO堆栈中的DMA写入之后的任何DMA访问一起停滞。 DMA读取访问不进行比较，但可能会停滞在DMA写入访问失败之后。 如果缓存读取可能可缓存，则会出现这些停顿。 这对某些受监视的访问是可能的，但不是全部。 如果DMA写入停止，则只要没有待处理的读取到相同的高速缓存行，比较器将释放它。
-
22.发明授权Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance 有权增强了二级缓存控制器的流水线和多缓冲架构，以最大限度地减少危害档位并优化性能公开(公告)号：US08732398B2
公开(公告)日：2014-05-20
申请号：US13245211
申请日：2011-09-26
IPC分类号： G06F13/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.
摘要翻译： 本发明是包括中央处理单元，外部接口，一级缓存，包括二级统一缓存的二级存储器和直接可寻址存储器的数据处理系统。 二级存储器控制器包括可直接寻址的存储器读取流水线，中央处理单元写入流水线，外部可缓存流水线和外部非缓存流水线。
-
23.发明授权Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers 有权优化从一级的二级缓存系统中的标签转发，以便两个控制器用于直接内存访问传输的缓存一致性协议公开(公告)号：US08656105B2
公开(公告)日：2014-02-18
申请号：US13245206
申请日：2011-09-26
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
-
24.发明授权Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty 有权在一级数据缓存和行中引起的二级组合高速缓存/ SRAM的DMA写入的性能和电源改进是有效和脏的公开(公告)号：US09075744B2
公开(公告)日：2015-07-07
申请号：US13245183
申请日：2011-09-26
申请人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
发明人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
IPC分类号： G06F12/08 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.
摘要翻译： 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。
-
公开(公告)号：US08683137B2
公开(公告)日：2014-03-25
申请号：US13247222
申请日：2011-09-28
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request according to said least recently used indication of said ways and then update the least recently used indication of remaining ways of the set. This permits read allocate requests to the same set to proceed without introducing processing stalls due to way contention. This also allows multiple outstanding allocate requests to the same set and way combination. The cache also compares the address of a newly received allocation request to stall this allocation request if the address matches an address of any pending allocation request.
摘要翻译： 本发明是一种具有数据高速缓存的数据处理系统。 高速缓存控制器通过根据所述最近最近使用的所述方式的指示预先分配组中的方式来响应要求分配的高速缓存未命中，然后更新所述组的剩余方式的最近最少使用的指示。 这允许对同一集合的读取分配请求进行，而不会因为方式争用而引入处理分摊。 这也允许多个未完成的分配请求以相同的集合和方式组合。 如果地址与任何待处理的分配请求的地址相匹配，高速缓存还会比较新接收到的分配请求的地址以停止该分配请求。
-
26.发明授权Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU 有权通过根据CPU所需的字节优化分配命令的大小和顺序，实现高效的缓存分配公开(公告)号：US08607000B2
公开(公告)日：2013-12-10
申请号：US13243411
申请日：2011-09-23
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
摘要翻译： 本发明是一种具有多级缓存系统的数据处理系统。 多级缓存系统至少包括第一级缓存和第二级高速缓存。 在所述至少一个第一级高速缓存和所述第二级高速缓存中的高速缓存未命中时，所述数据处理系统在所述第二级高速缓存内驱逐并分配高速缓存行。 数据处理系统从未命中地址确定请求是否落在所分配的高速缓存行的低一半或高一半内。 数据处理系统首先从缺失半高速缓存行的外部存储器请求数据。 当接收数据被提供给至少一个第一级高速缓存和CPU时。 数据处理系统然后从第二级高速缓存行的另一半请求来自外部存储器的数据。
-
27.发明申请Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence 有权缓存受害者和回写期间保持一级数据缓存和二级缓存一致性的一级数据高速缓存行锁和增强型侦听协议公开(公告)号：US20120198163A1
公开(公告)日：2012-08-02
申请号：US13247209
申请日：2011-09-28
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.
摘要翻译： 本发明在驱逐较高级别的高速缓存行时确保多级高速缓存系统中的高速缓存一致性。 受害者缓冲区将数据存储在被驱逐的行上。 在可能缓存在较高级别缓存中的DMA访问中，下级缓存发送窥探写。 将该窥探写的地址与受害缓冲区进行比较。 在受害缓冲区中的命中，写入在受害缓冲区中完成。 当受害者数据传递到下一个缓存级别时，当数据被提交到高速缓存时，它被写入第二个受害缓冲区以便退出。 DMA写地址与第二个受害缓冲区中的地址进行比较。 在匹配中，写入发生在第二个受害缓冲区中。 在无法匹配的情况下，控制器发出一个窥探写。
-
28.发明申请NON-BLOCKING, PIPELINED WRITE ALLOCATES WITH ALLOCATE DATA MERGING IN A MULTI-LEVEL CACHE SYSTEM 有权非阻塞，多级写入分配与多级缓存系统中的分配数据合并公开(公告)号：US20120198161A1
公开(公告)日：2012-08-02
申请号：US13245178
申请日：2011-09-26
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data returned from the external memory and stores merged data in the cache. The cache controller includes buffers with plural entries storing the write address, the write data, the position of the write data within a cache line and unique identification number. This stored data enables the cache controller to proceed to servicing other access requests while waiting for response from the external memory.
摘要翻译： 本发明处理写请求高速缓存未命中。 高速缓存控制器存储写入数据，向对应的高速缓存线的外部存储器发送读取请求，将写入数据与从外部存储器返回的数据合并，并将合并的数据存储在高速缓存中。 高速缓存控制器包括具有存储写入地址，写入数据，高速缓存行中的写入数据的位置和唯一标识号的多个条目的缓冲器。 该存储的数据使高速缓存控制器能够在等待来自外部存储器的响应的同时继续服务其他访问请求。
-
29.发明申请Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme 有权使用双银行内存方案的多级缓存系统中的软错误检测，更正和报告的强大汉明码实现公开(公告)号：US20120192027A1
公开(公告)日：2012-07-26
申请号：US13243370
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
摘要翻译： 本发明是一种具有两个存储体的存储器系统，其可以存储和调用具有两种不同尺寸的数据的存储器错误检测和校正。 为单独的奇偶校验生成器形成相应存储体的奇偶校验位。 用于读取单独的奇偶检测器/发生器对单独存储体的数据进行操作。
-
30.发明申请OPTIMIZING TAG FORWARDING IN A TWO LEVEL CACHE SYSTEM FROM LEVEL ONE TO LEVER TWO CONTROLLERS FOR CACHE COHERENCE PROTOCOL FOR DIRECT MEMORY ACCESS TRANSFERS 有权优化标签在两级高速缓存系统中从一级到两级控制器，用于直接存储器访问传输的高速缓存协议协议公开(公告)号：US20120191916A1
公开(公告)日：2012-07-26
申请号：US13245206
申请日：2011-09-26
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.025 秒)
