公开(公告)号：US20120147644A1

公开(公告)日：2012-06-14

申请号：US13323680

申请日：2011-12-12

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C5/02 ,  H01L21/336

CPC分类号： G11C13/0033 ,  G11C5/025 ,  G11C8/08 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/165 ,  H01L45/1683

摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

摘要翻译： 适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

公开(公告)号：US20120140546A1

公开(公告)日：2012-06-07

申请号：US13396489

申请日：2012-02-14

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.

公开(公告)号：US20120135580A1

公开(公告)日：2012-05-31

申请号：US13365991

申请日：2012-02-03

申请人： Roy E. Scheuerlein ,  Eliyahou Harari

发明人： Roy E. Scheuerlein ,  Eliyahou Harari

IPC分类号： H01L45/00

CPC分类号： G11C13/0007 ,  G11C13/0004 ,  G11C13/0011 ,  G11C17/16 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/35 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1675

摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

摘要翻译： 公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。 共享支柱结构包括两个非易失性存储元件。 每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。 每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。 每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。 各个存储元件各自包括转向元件和状态改变元件。

公开(公告)号：US20120044733A1

公开(公告)日：2012-02-23

申请号：US12938028

申请日：2010-11-02

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C7/12 ,  H01L21/02 ,  G11C5/02

CPC分类号： G11C13/0026 ,  B82Y10/00 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/025 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/0688

摘要： A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.

摘要翻译： 存储器件包括耦合在位和字线之间的二极管加电阻率开关元件存储单元，单个器件位线驱动器，其栅极耦合到位线解码器控制引线，耦合到位线驱动器的源极/漏极以及耦合到 位线，具有耦合到字线解码器控制引线的栅极的单器件字线驱动器，耦合到字线驱动器输出的源极/漏极以及耦合到字线的漏极/源极，耦合在位线和位线之间的第一泄放二极管 第一泄放二极管控制器和耦合在字线和第二泄放二极管控制器之间的第二泄放二极管。 第一泄放二极管控制器响应于位线解码器信号将第一泄放二极管连接到低电压。 第二泄放二极管控制器响应于字线解码器信号将第二泄放二极管连接到高电压。

公开(公告)号：US08102698B2

公开(公告)日：2012-01-24

申请号：US12952944

申请日：2010-11-23

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/21 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481

摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

摘要翻译： 具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。 因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。 为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。 改进的电流镜结构控制相变材料的状态切换。

公开(公告)号：US08094510B2

公开(公告)日：2012-01-10

申请号：US12847378

申请日：2010-07-30

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C5/025 ,  G11C7/067 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C17/18 ,  G11C2207/063

摘要： A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

摘要翻译： 存储器阵列包括用于感测位线电流的感测电路，同时保持所选位线的电压基本上不变。 字线和位线被偏置，使得基本上不会在半选择的存储器单元上施加偏置电压，这几乎消除了通过半选择的存储器单元的泄漏电流。 感测的位线电流很大程度上仅来自所选存储单元的电流。 存储器阵列中的噪声检测线减少了从未选择的字线耦合到所选位线的影响。 在优选实施例中，具有在多于一个层上形成位线的多个轨道堆叠的三维存储器阵列包括与每个位线层相关联的至少一个噪声检测线。 感测电路连接到选定的位线及其相关的噪声检测线。

公开(公告)号：US20110299354A1

公开(公告)日：2011-12-08

申请号：US13215134

申请日：2011-08-22

申请人： Roy E. Scheuerlein ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Luca G. Fasoli

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  Y10T29/49002

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US20110292751A1

公开(公告)日：2011-12-01

申请号：US13205820

申请日：2011-08-09

申请人： Tyler Thorp ,  Roy E. Scheuerlein

发明人： Tyler Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C16/06

摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.

摘要翻译： 提供了用于存储器集成电路（“IC”）的热调节的装置和系统。 该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。 加热元件适于响应于来自热传感器的信号来加热存储器IC。 还提供其他方面。

公开(公告)号：US20110266514A1

公开(公告)日：2011-11-03

申请号：US13182960

申请日：2011-07-14

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： H01L45/00 ,  B82Y99/00

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.

摘要翻译： 提供了一种存储单元，所述存储单元包括具有垂直取向的p-i-n结的转向元件和碳纳米管织物。 导向元件和碳纳米管织物电串联布置，整个存储单元形成在基板上。 还提供其他方面。

公开(公告)号：US08040721B2

公开(公告)日：2011-10-18

申请号：US12551546

申请日：2009-08-31

申请人： Tyler Thorp ,  Roy E. Scheuerlein

发明人： Tyler Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/77

摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, switching the first line from the first voltage to a second voltage, and switching the first line from the second voltage to the first voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. The switching operations together may create a first pulse.

摘要翻译： 本发明提供了用于调整位和字线的电压以产生编程脉冲以编程存储器单元的方法和装置。 本发明可以包括将连接到存储器单元的第一线路从第一线路备用电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，将第一线路从 第一电压到第二电压，并且将第一线路从第二电压切换到第一电压。 第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。 第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。 一起切换操作可以产生第一脉冲。