公开(公告)号：US20210305096A1

公开(公告)日：2021-09-30

申请号：US17304136

申请日：2021-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： George CHANG ,  Yusheng LIN ,  Gordon M. GRIVNA ,  Takashi NOMA

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

公开(公告)号：US20190148306A1

公开(公告)日：2019-05-16

申请号：US16229186

申请日：2018-12-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Shinzo ISHIBE ,  Kazuyuki SUTO

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/265 ,  H01L29/861 ,  H01L29/739 ,  H01L21/324 ,  H01L23/528 ,  H01L21/22 ,  H01L21/28 ,  H01L23/482 ,  H01L21/304

Abstract: Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer.

公开(公告)号：US20180053739A1

公开(公告)日：2018-02-22

申请号：US15240568

申请日：2016-08-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00

CPC classification number: H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13026

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20220285267A1

公开(公告)日：2022-09-08

申请号：US17249436

申请日：2021-03-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Yusheng LIN

IPC: H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a back side and a front side, the back side being coupled with a base, the front side including active circuitry. The assembly can include a first resin encapsulation layer disposed on a first portion of the front side. The first resin encapsulation layer can be patterned to define a first opening exposing a second portion of the front side through the first resin encapsulation layer. The assembly can include a signal distribution structure that is disposed on the first resin encapsulation layer, and electrically coupled with the front side through the first opening. The assembly can include a second resin encapsulation layer disposed on a first portion of the signal distribution structure, the second resin encapsulation layer being patterned to define a second opening that exposes a second portion of the signal distribution structure.

公开(公告)号：US20220131002A1

公开(公告)日：2022-04-28

申请号：US16949321

申请日：2020-10-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Yusheng LIN ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Shunsuke YASUDA

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66

Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.

公开(公告)号：US20220028812A1

公开(公告)日：2022-01-27

申请号：US17450007

申请日：2021-10-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  H01L21/48

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20210118675A1

公开(公告)日：2021-04-22

申请号：US17134717

申请日：2020-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Michael J. SEDDON

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/78 ,  H01L21/3213

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

公开(公告)号：US20210028051A1

公开(公告)日：2021-01-28

申请号：US16661686

申请日：2019-10-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Noboru OKUBO ,  Yusheng LIN

IPC: H01L21/687 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L29/861 ,  H01L29/739

Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

公开(公告)号：US20200243392A1

公开(公告)日：2020-07-30

申请号：US16506004

申请日：2019-07-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA

IPC: H01L21/78 ,  H01L21/66 ,  H01L21/304 ,  H01L21/683 ,  H01L21/02 ,  H01L21/3205

Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

公开(公告)号：US20200243367A1

公开(公告)日：2020-07-30

申请号：US16505967

申请日：2019-07-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA

IPC: H01L21/68 ,  H01L21/78 ,  H01L21/768

Abstract: Implementations of a method for wafer alignment may include: providing a wafer having a first side and a second side and forming a seed layer on a second side of the wafer. The method may include applying a glop to the seed layer at two or more predetermined points and plating a metal layer over the seed layer and around the glop. The method may include removing the glop to expose the seed layer and etching the seed layer to expose a plurality of alignment features on the second side of the wafer.