公开(公告)号：US20170005659A1

公开(公告)日：2017-01-05

申请号：US15189034

申请日：2016-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: H03K19/00 ,  H01L29/786 ,  H03K19/017

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L29/7869 ,  H03K19/017

Abstract: The drive capability of a logic circuit is improved. The logic circuit includes a first output node, a dynamic logic circuit, a diode-connected first transistor, and a capacitor. The dynamic logic circuit includes a second output node and a plurality of second transistors forming and evaluation circuit. The first transistor and the plurality of second transistors all have one of an n-type conductivity and a p-type conductivity. One terminal of the capacitor is electrically connected to the first output node. The other terminal of the capacitor is electrically connected to the second output node. A first terminal of the first transistor is electrically connected to the first output node. A first voltage is input to a second terminal of the first transistor. The voltage of the first output node is changed by a voltage applied to a back gate of the first transistor.

Abstract translation: 提高了逻辑电路的驱动能力。 逻辑电路包括第一输出节点，动态逻辑电路，二极管连接的第一晶体管和电容器。 动态逻辑电路包括第二输出节点和多个第二晶体管形成和评估电路。 第一晶体管和多个第二晶体管都具有n型导电性和p型导电性之一。 电容器的一个端子电连接到第一输出节点。 电容器的另一个端子电连接到第二输出节点。 第一晶体管的第一端子电连接到第一输出节点。 第一电压被输入到第一晶体管的第二端子。 第一输出节点的电压通过施加到第一晶体管的背栅极的电压而改变。

公开(公告)号：US20170005658A1

公开(公告)日：2017-01-05

申请号：US15199004

申请日：2016-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H03K19/00 ,  H03K3/037 ,  H01L29/04 ,  H01L27/108 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract translation: 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

公开(公告)号：US20160105174A1

公开(公告)日：2016-04-14

申请号：US14874607

申请日：2015-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H03K19/00 ,  H01L49/02 ,  H01L29/04 ,  H01L27/12 ,  H03K19/0185 ,  H01L29/78

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract translation: 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

公开(公告)号：US20150348975A1

公开(公告)日：2015-12-03

申请号：US14719789

申请日：2015-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1052 ,  H01L27/1156

Abstract: A low-power-consuming semiconductor device that can store analog data stably and very accurately is provided at low cost. The semiconductor device includes a power supply portion, a sensor portion, and a memory element portion. The sensor portion acquires analog data. The memory element portion stores the analog data. A channel formation region of a transistor included in the memory element portion is formed in an oxide semiconductor film. The semiconductor device does not include an analog/digital converter circuit and has functions of measuring and storing analog data.

Abstract translation: 以低成本提供可以稳定且非常准确地存储模拟数据的低功耗半导体器件。 半导体器件包括电源部分，传感器部分和存储元件部分。 传感器部分获取模拟数据。 存储元件部分存储模拟数据。 包含在存储元件部分中的晶体管的沟道形成区域形成在氧化物半导体膜中。 半导体器件不包括模拟/数字转换器电路，并且具有测量和存储模拟数据的功能。

公开(公告)号：US20240006424A1

公开(公告)日：2024-01-04

申请号：US18232424

申请日：2023-08-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA

IPC: H01L27/146 ,  G09G3/36 ,  H01L29/786

CPC classification number: H01L27/14603 ,  G09G3/3648 ,  H01L27/14641 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  G09G2354/00

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

公开(公告)号：US20220020793A1

公开(公告)日：2022-01-20

申请号：US17490009

申请日：2021-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20200013453A1

公开(公告)日：2020-01-09

申请号：US16572784

申请日：2019-09-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Hikaru TAMURA

IPC: G11C11/419 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4096 ,  H01L23/544 ,  H01L27/105 ,  H01L29/786

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

公开(公告)号：US20180082747A1

公开(公告)日：2018-03-22

申请号：US15823662

申请日：2017-11-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: G11C16/10 ,  G11C7/16 ,  G11C7/10 ,  G11C11/40

CPC classification number: G11C16/10 ,  G11C7/1078 ,  G11C7/16 ,  G11C11/40

Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

公开(公告)号：US20180018035A1

公开(公告)日：2018-01-18

申请号：US15644881

申请日：2017-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Shunpei YAMAZAKI

IPC: G06F3/042 ,  H01L27/146

CPC classification number: G06F3/042 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14692

Abstract: One object is to provide a new electronic device which is configured so that a user can read data regardless of a location, input data by directly touching a keyboard displayed on a screen or indirectly touching the keyboard with a stylus pen or the like, and use the input data. A first transistor electrically connected to a reflective electrode and a photo sensor are included over one substrate. A touch-input button displayed on a first screen region of the display portion is displayed as a still image, and a video signal is output so that a moving image is displayed on a second screen region of the display portion. A video signal processing portion supplying different signals between the case where a still image is displayed on the display portion and the case where a moving image is displayed on the display portion is included.

公开(公告)号：US20170221553A1

公开(公告)日：2017-08-03

申请号：US15415456

申请日：2017-01-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Hikaru TAMURA

IPC: G11C11/419 ,  H01L29/786 ,  H01L23/544 ,  H01L27/105

CPC classification number: G11C11/419 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229 ,  H01L23/544 ,  H01L27/1052 ,  H01L29/7869

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.