公开(公告)号：US09620186B2

公开(公告)日：2017-04-11

申请号：US15220469

申请日：2016-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Yasuyuki Takahashi

IPC: G11C8/00 ,  G11C7/22 ,  G11C8/10 ,  G11C5/06 ,  H01L29/786 ,  H01L27/12 ,  H01L27/105

CPC classification number: G11C7/22 ,  G11C5/06 ,  G11C8/10 ,  G11C11/404 ,  G11C16/02 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.

公开(公告)号：US20170004865A1

公开(公告)日：2017-01-05

申请号：US15125658

申请日：2015-03-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Tomoaki Atsumi ,  Shunpei Yamazaki

IPC: G11C7/22 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C11/405 ,  G11C11/565 ,  G11C27/005 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/786

Abstract: A semiconductor device which can write and read multilevel data is provided. Anode connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read.

Abstract translation: 提供了可以写入和读取多级数据的半导体器件。 连接OS晶体管的源极或漏极和OS晶体管的栅极的阳极可以保持多个电位的分布。 采用电路结构，其中通过电容耦合来改变节点的电位，以控制其栅极连接到其上的OS晶体管的导通状态，使得Si晶体管的栅极的电位改变。 Si晶体管的栅极的电位根据电容耦合的电位变化而正向变化，并根据另一个晶体管呈负变化。 根据检测到流过Si晶体管的电流值的变化，读取写入的数据。

公开(公告)号：US09525051B2

公开(公告)日：2016-12-20

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/00 ,  H01L29/66 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09472293B2

公开(公告)日：2016-10-18

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

公开(公告)号：US20160203871A1

公开(公告)日：2016-07-14

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US09007813B2

公开(公告)日：2015-04-14

申请号：US13795244

申请日：2013-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24 ,  H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12

CPC classification number: H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

Abstract translation: 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

公开(公告)号：US20150084046A1

公开(公告)日：2015-03-26

申请号：US14492412

申请日：2014-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Hidekazu Miyairi ,  Shuhei Nagatsuka

IPC: H01L27/06 ,  H01L29/24

CPC classification number: H01L27/0629 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255

Abstract: A semiconductor device including a transistor and a capacitor which occupies a small area is provided. The semiconductor device includes a semiconductor, first and second conductive films each comprising a region in contact with top and side surfaces of the semiconductor, a first insulating film comprising a region in contact with the top and side surfaces of the semiconductor, a third conductive film comprising a region facing the top and side surfaces of the semiconductor with the first insulating film therebetween, a second insulating film which is in contact with the first conductive film and comprises an opening, a fourth conductive film comprising a region in contact with the opening, a third insulating film comprising a region facing the opening with the fourth conductive film therebetween, and a fifth conductive film comprising a region facing the fourth conductive film with the third insulating film therebetween.

Abstract translation: 提供了包括占据小面积的晶体管和电容器的半导体器件。 半导体器件包括半导体，第一和第二导电膜，每个包括与半导体的顶表面和侧表面接触的区域;第一绝缘膜，包括与半导体的顶表面和侧表面接触的区域;第三导电膜 包括面对半导体的顶表面和侧表面的区域，其间具有第一绝缘膜，与第一导电膜接触并包括开口的第二绝缘膜，包括与开口接触的区域的第四导电膜， 第三绝缘膜，其包括与其间具有第四导电膜的开口面对的区域;以及第五导电膜，其包括面对第四导电膜的区域，其间具有第三绝缘膜。

公开(公告)号：US08542004B2

公开(公告)日：2013-09-24

申请号：US13683863

申请日：2012-11-21

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G01R19/00

CPC classification number: G11C11/24 ,  G11C11/403 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.

Abstract translation: 目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。 半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。 因此，可以充分降低半导体器件的功耗。

公开(公告)号：US20130221344A1

公开(公告)日：2013-08-29

申请号：US13768743

申请日：2013-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Shuhei Nagatsuka

IPC: H01L29/786 ,  H01L27/088

CPC classification number: H01L29/786 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/0315 ,  H03K19/0013 ,  H03K19/20 ,  H03K2005/00032 ,  H03K2005/00195 ,  H03K2217/0018

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract translation: 为了提供一种半导体器件，其包括通过控制晶体管的阈值电压或包括具有低功耗的入侵电路的半导体器件来驱动驱动频率的逆变器电路。 逆变器电路包括第一晶体管和第二晶体管，每个晶体管和第二晶体管都包括其中形成沟道的半导体膜，放置半导体膜的一对栅极电极和与半导体膜接触的源极和漏极。 施加到一对栅电极的控制电位使得第一晶体管具有常开特性，而第二晶体管具有常关特性。 因此，逆变器电路的驱动频率增加。

公开(公告)号：US12300794B2

公开(公告)日：2025-05-13

申请号：US18596899

申请日：2024-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H01M10/44 ,  H02J7/00 ,  H02J50/10 ,  H02J50/27 ,  H02J50/40 ,  H04B1/3883

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.