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公开(公告)号：US20180254352A1
公开(公告)日：2018-09-06
申请号：US15904867
申请日：2018-02-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Junichi KOEZUKA , Kenichi OKAZAKI , Yukinori SHIMA , Yasutaka NAKAZAWA , Yasuharu HOSAKA , Shunpei YAMAZAKI
IPC: H01L29/786 , H01L29/24 , H01L29/66 , H01L21/02 , H01L27/12
CPC classification number: H01L29/78696 , G02F1/1333 , G02F1/13338 , G02F1/1368 , G02F2001/13685 , G06F3/0412 , G06F3/044 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/0296 , H01L27/1225 , H01L27/1259 , H01L27/127 , H01L27/3262 , H01L29/24 , H01L29/66969 , H01L29/78606 , H01L29/78648 , H01L29/7869
Abstract: A semiconductor device with favorable electrical characteristics is to be provided. A highly reliable semiconductor device is to be provided. A semiconductor device with lower power consumption is to be provided. The semiconductor device includes a gate electrode, a first insulating layer over the gate electrode, a metal oxide layer over the first insulating layer, a pair of electrodes over the metal oxide layer, and a second insulating layer over the pair of electrodes. The first insulating layer includes a first region and a second region. The first region has a region being in contact with the metal oxide layer and containing more oxygen than the second region. The second region has a region containing more nitrogen than the first region. The metal oxide layer has at least a concentration gradient of oxygen in a thickness direction, and the concentration gradient becomes high on a first region side and on a second region side.
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公开(公告)号：US20180197888A1
公开(公告)日：2018-07-12
申请号：US15904537
申请日：2018-02-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki MIYAKE , Kenichi OKAZAKI , Yasuharu HOSAKA , Yukinori SHIMA
IPC: H01L27/12 , H01L51/00 , H01L29/786 , H01L29/778 , H01L29/66 , H01L29/24 , H01L29/04 , H01L27/32
CPC classification number: H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/045 , H01L29/24 , H01L29/66969 , H01L29/7782 , H01L29/7786 , H01L29/78606 , H01L29/78648 , H01L29/7869 , H01L29/78696 , H01L51/005
Abstract: Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film. The second transistor comprises a first drain electrode; the second insulating film over the second drain electrode; a second oxide semiconductor film over the second insulating film; a second source electrode and a second drain electrode over the second oxide semiconductor film; a third insulating film over the second oxide semiconductor film, the second source electrode, and the second drain electrode; and a third gate electrode over the third insulating film. The first oxide semiconductor film partly overlaps with the second oxide semiconductor film.
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公开(公告)号：US20170186778A1
公开(公告)日：2017-06-29
申请号：US15386649
申请日：2016-12-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki MIYAKE , Kenichi OKAZAKI , Yasuharu HOSAKA , Yukinori SHIMA
CPC classification number: H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/045 , H01L29/24 , H01L29/66969 , H01L29/7782 , H01L29/7786 , H01L29/78606 , H01L29/78648 , H01L29/7869 , H01L29/78696 , H01L51/005
Abstract: Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film. The second transistor comprises a first drain electrode; the second insulating film over the second drain electrode; a second oxide semiconductor film over the second insulating film; a second source electrode and a second drain electrode over the second oxide semiconductor film; a third insulating film over the second oxide semiconductor film, the second source electrode, and the second drain electrode; and a third gate electrode over the third insulating film. The first oxide semiconductor film partly overlaps with the second oxide semiconductor film.
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公开(公告)号：US20170154902A1
公开(公告)日：2017-06-01
申请号：US15428285
申请日：2017-02-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shingo EGUCHI , Yohei MONMA , Atsuhiro TANI , Misako HIROSUE , Kenichi HASHIMOTO , Yasuharu HOSAKA
CPC classification number: H01L27/1266 , B32B43/006 , G02F1/1303 , G02F1/13306 , G06K19/0772 , H01L21/67132 , H01L21/6835 , H01L27/1214 , H01L27/1218 , H01L27/156 , H01L31/1892 , H01L31/206 , H01L33/005 , H01L51/003 , H01L51/0097 , H01L2221/68318 , H01L2221/6835 , H01L2221/68363 , H01L2221/68386 , H01L2221/68395 , H01L2227/326 , H01L2251/5338 , H01L2924/19041 , H01L2924/30105 , Y10T29/41
Abstract: To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid.
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公开(公告)号：US20160314999A1
公开(公告)日：2016-10-27
申请号：US15204091
申请日：2016-07-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shingo EGUCHI , Yohei MONMA , Atsuhiro TANI , Misako HIROSUE , Kenichi HASHIMOTO , Yasuharu HOSAKA
IPC: H01L21/67 , H01L21/683 , B32B43/00 , H01L27/12
CPC classification number: H01L27/1266 , B32B43/006 , G02F1/1303 , G02F1/13306 , G06K19/0772 , H01L21/67132 , H01L21/6835 , H01L27/1214 , H01L27/1218 , H01L27/156 , H01L31/1892 , H01L31/206 , H01L33/005 , H01L51/003 , H01L51/0097 , H01L2221/68318 , H01L2221/6835 , H01L2221/68363 , H01L2221/68386 , H01L2221/68395 , H01L2227/326 , H01L2251/5338 , H01L2924/19041 , H01L2924/30105 , Y10T29/41
Abstract: To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20160027924A1
公开(公告)日：2016-01-28
申请号：US14875101
申请日：2015-10-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Toshinari SASAKI , Hiroshi KANEMURA , Yasuharu HOSAKA , Shuhei YOKOYAMA , Toshimitsu OBONAI
IPC: H01L29/786
CPC classification number: H01L29/7869 , G01R31/2656 , G09G3/006 , G09G3/3225 , G09G3/3648 , H01L27/14678 , H01L27/14692 , H01L29/22
Abstract: A semiconductor layer with a low density of trap states is provided. A transistor with stable electrical characteristics is provided. A transistor having high field-effect mobility is provided. A semiconductor device including the transistor is provided. A method for evaluating a semiconductor layer is provided. A method for evaluating a transistor is provided. A method for evaluating a semiconductor device is provided. Provided is, for example, a semiconductor layer with a low defect density which can be used for a channel formation region of a transistor, a transistor including a semiconductor layer with a low defect density in a channel formation region, or a semiconductor device including the transistor.
Abstract translation: 提供了具有低密度陷阱状态的半导体层。 提供具有稳定电特性的晶体管。 提供具有高场效应迁移率的晶体管。 提供包括晶体管的半导体器件。 提供了一种用于评估半导体层的方法。 提供了一种用于评估晶体管的方法。 提供了一种用于评估半导体器件的方法。 例如，提供了可以用于晶体管的沟道形成区域的具有低缺陷密度的半导体层，在沟道形成区域中包括具有低缺陷密度的半导体层的晶体管，或包括晶体管的半导体器件 晶体管。
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公开(公告)号：US20150102341A1
公开(公告)日：2015-04-16
申请号：US14505004
申请日：2014-10-02
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Yasuharu HOSAKA , Toshimitsu OBONAI , Junichi KOEZUKA , Yukinori SHIMA , Masahiko HAYAKAWA , Takashi HAMOCHI , Suzunosuke HIRAISHI
IPC: H01L29/786 , H01L29/24
CPC classification number: H01L21/477 , H01L21/02112 , H01L21/02403 , H01L21/28 , H01L29/24 , H01L29/78606 , H01L29/7869
Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
Abstract translation: 为了抑制电特性的改变，并提高使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的栅电极，与栅电极重叠的氧化物半导体膜，位于栅电极和氧化物半导体膜之间并与氧化物半导体膜的表面接触的栅极绝缘膜， 与氧化物半导体膜的表面的相对表面接触的保护膜和与氧化物半导体膜接触的一对电极。 在栅极绝缘膜或保护膜中，通过热处理释放的质荷比为m / z为17的气体的量比通过热处理释放的氮氧化物的量大。
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公开(公告)号：US20150017751A1
公开(公告)日：2015-01-15
申请号：US14339867
申请日：2014-07-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shingo EGUCHI , Yohei MONMA , Atsuhiro TANI , Misako HIROSUE , Kenichi HASHIMOTO , Yasuharu HOSAKA
CPC classification number: H01L21/67132 , H01L21/02244 , H01L21/02252 , H01L21/67092 , H01L21/707 , H01L27/1266
Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
Abstract translation: 当从衬底剥离包括半导体元件的元件形成层时，目的是抑制由剥离产生的静电产生的放电。 在衬底上形成释放层和元件形成层。 可以将后面剥离的支撑基材固定在元件形成层的上表面。 元件形成层通过支撑基材转变，并且在元件形成层和剥离层之间的界面产生剥离。 在供给液体时进行剥离，使得通过剥离顺序出现的元素形成层和剥离层用诸如纯水的液体润湿。 在元件形成层和剥离层的表面上产生的电荷可以被液体扩散，并且可以消除通过剥离带电的放电。
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公开(公告)号：US20140374745A1
公开(公告)日：2014-12-25
申请号：US14303629
申请日：2014-06-13
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Hironobu TAKAHASHI , Yukinori SHIMA , Yasuharu HOSAKA , Toshimitsu OBONAI , Masashi TSUBUKU
IPC: H01L27/146 , H01L29/786
CPC classification number: H01L27/14663 , H01L27/14616 , H01L27/14625 , H01L27/14692 , H01L29/42384 , H01L29/4908 , H01L29/7869 , H04N5/3745
Abstract: An imaging device that is highly stable to irradiation with radial rays such as X-rays and can inhibit a decrease in electrical characteristics is provided. The imaging device takes an image with radial rays such as X-rays and includes pixel circuits arranged in a matrix and a scintillator overlapping the pixel circuits. The pixel circuits each includes a switching transistor with an extremely small off-state current and a light-receiving element which is configured to convert the radial rays to electrical charges. A gate insulating film of the switching transistor has a stacked structure including a silicon nitride film with a thickness of 100 nm to 400 nm and a silicon oxide film or a silicon oxynitride film with a thickness of 5 nm to 20 nm.
Abstract translation: 提供了对X射线等径向射线照射高度稳定的成像装置，能够抑制电特性的降低。 成像装置拍摄具有诸如X射线的径向射线的图像，并且包括以矩阵布置的像素电路和与像素电路重叠的闪烁体。 像素电路各自包括非常小的截止电流的开关晶体管和被配置为将径向射线转换成电荷的光接收元件。 开关晶体管的栅极绝缘膜具有包括厚度为100nm至400nm的氮化硅膜和厚度为5nm至20nm的氧化硅膜或氮氧化硅膜的叠层结构。
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公开(公告)号：US20250160123A1
公开(公告)日：2025-05-15
申请号：US18835069
申请日：2023-03-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yasuharu HOSAKA , Yukinori SHIMA , Masami JINTYOU , Masataka NAKADA , Junichi KOEZUKA , Kenichi OKAZAKI
IPC: H10K59/121 , H10K59/12
Abstract: A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer including a region overlapping with the first conductive layer with the first insulating layer therebetween, a third conductive layer, and a third insulating layer. The second conductive layer and the first insulating layer have a first opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, and a top surface of the first conductive layer. The third insulating layer is provided over the first insulating layer, the first semiconductor layer, and the second conductive layer. The third conductive layer is provided over the third insulating layer. The second insulating layer is provided over the third conductive layer and the third insulating layer.
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