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21.发明授权公开(公告)号：US10964382B2
公开(公告)日：2021-03-30
申请号：US16296796
申请日：2019-03-08
Applicant: SK hynix Inc.
Inventor： Ki Won Lee , Seok Man Hong , Tae Hoon Kim , Hyung Dong Lee
IPC: G11C13/00
Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
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公开(公告)号：US10825519B1
公开(公告)日：2020-11-03
申请号：US16687384
申请日：2019-11-18
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.
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23.发明授权公开(公告)号：US10685714B2
公开(公告)日：2020-06-16
申请号：US16168380
申请日：2018-10-23
Applicant: SK hynix Inc.
Inventor： Ji Man Hong , Tae Hoon Kim
Abstract: Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.
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24.发明授权公开(公告)号：US10050019B2
公开(公告)日：2018-08-14
申请号：US15405619
申请日：2017-01-13
Applicant: SK hynix Inc.
Inventor： Tae Hoon Kim , Jong Hoon Kim , Dae Won Kim , Hyeong Seok Choi
IPC: H01L23/48 , H01L25/065 , H01L21/56 , H01L21/768 , H01L23/29 , H01L23/31 , H01L23/00 , H01L25/00
Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.
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25.发明授权公开(公告)号：US08941406B2
公开(公告)日：2015-01-27
申请号：US13720992
申请日：2012-12-19
Applicant: SK Hynix Inc.
Inventor： Sung Woo Han , Ic Su Oh , Jun Ho Lee , Boo Ho Jung , Sun Ki Cho , Yang Hee Kim , Tae Hoon Kim
CPC classification number: H03K3/013 , G06F17/5022 , H03K5/12
Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.
Abstract translation: 提供了一种减少包括多个输出缓冲器以输出数据的半导体装置的输出数据噪声的方法。 该方法包括以下步骤：将低数据驱动到多个输出缓冲器中的特定输出缓冲器，以及驱动数据从高电平转移到低电平到另一个输出缓冲器; 以及测量在特定输出缓冲器的输出数据中发生的数据噪声的大小，以及基于测量结果确定多个输出缓冲器的转换速率。
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Patent Agency Ranking
公开(公告)号：US08873300B2
公开(公告)日：2014-10-28
申请号：US13716412
申请日：2012-12-17
Applicant: SK hynix Inc.
Inventor： Tae Hoon Kim
CPC classification number: G11C7/00 , G11C11/56 , G11C11/5628
Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory cells having first to fourth middle states corresponding to different threshold voltage distributions. The semiconductor memory device also includes a peripheral circuit configured to perform a first program operation to program memory cells having the third and the fourth middle states to have four upper states and perform a second program operation to program memory cells having the first and the second middle states to have another four upper states.
Abstract translation: 提供半导体存储器件。 半导体存储器件包括具有对应于不同阈值电压分布的第一至第四中间状态的存储器单元。 半导体存储器件还包括外围电路，其被配置为执行第一编程操作以对具有第三和第四中间状态的存储单元编程以具有四个上状态，并执行第二编程操作以对具有第一和第二中间状态的存储单元 说有另外四个上层州。
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公开(公告)号：US12107077B2
公开(公告)日：2024-10-01
申请号：US18103968
申请日：2023-01-31
Applicant: SK hynix Inc.
Inventor： Tae Hoon Kim
IPC: H01L25/065
CPC classification number: H01L25/0657 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06593
Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.
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公开(公告)号：US11930647B2
公开(公告)日：2024-03-12
申请号：US17878678
申请日：2022-08-01
Applicant: SK hynix Inc.
Inventor： Si Jung Yoo , Tae Hoon Kim , Hyung Dong Lee
CPC classification number: H10B63/845 , H10B61/00 , H10N50/01 , H10N50/80 , H10N70/066 , H10N70/841
Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
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公开(公告)号：US11264095B2
公开(公告)日：2022-03-01
申请号：US17039480
申请日：2020-09-30
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.
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公开(公告)号：US10008289B2
公开(公告)日：2018-06-26
申请号：US15211862
申请日：2016-07-15
Applicant: SK hynix Inc.
Inventor： Tae Hoon Kim
IPC: G11C29/50 , G11C16/34 , G11C16/26 , G11C11/56 , G11C16/14 , G11C29/12 , G11C29/36 , G11C29/38 , G11C29/44
CPC classification number: G11C29/50004 , G11C11/5642 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C29/12005 , G11C29/36 , G11C29/38 , G11C29/44 , G11C2029/5004
Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.
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