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公开(公告)号：US20220069813A1
公开(公告)日：2022-03-03
申请号：US17171719
申请日：2021-02-09
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Dong Uc Ko , Yang Ho Sur , Jun Yong Song , Sung Gil Jang , Hae Kang Jung , Min Sung Cheon , Chang Kyu Choi , Tae Jin Hwang
Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.
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2.发明授权公开(公告)号：US10742182B2
公开(公告)日：2020-08-11
申请号：US16209650
申请日：2018-12-04
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Dae Han Kwon
Abstract: A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.
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公开(公告)号：US11271553B1
公开(公告)日：2022-03-08
申请号：US17171719
申请日：2021-02-09
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Dong Uc Ko , Yang Ho Sur , Jun Yong Song , Sung Gil Jang , Hae Kang Jung , Min Sung Cheon , Chang Kyu Choi , Tae Jin Hwang
Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.
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4.发明授权公开(公告)号：US08941406B2
公开(公告)日：2015-01-27
申请号：US13720992
申请日：2012-12-19
Applicant: SK Hynix Inc.
Inventor： Sung Woo Han , Ic Su Oh , Jun Ho Lee , Boo Ho Jung , Sun Ki Cho , Yang Hee Kim , Tae Hoon Kim
CPC classification number: H03K3/013 , G06F17/5022 , H03K5/12
Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.
Abstract translation: 提供了一种减少包括多个输出缓冲器以输出数据的半导体装置的输出数据噪声的方法。 该方法包括以下步骤：将低数据驱动到多个输出缓冲器中的特定输出缓冲器，以及驱动数据从高电平转移到低电平到另一个输出缓冲器; 以及测量在特定输出缓冲器的输出数据中发生的数据噪声的大小，以及基于测量结果确定多个输出缓冲器的转换速率。
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公开(公告)号：US09865318B2
公开(公告)日：2018-01-09
申请号：US15286722
申请日：2016-10-06
Applicant: SK hynix Inc.
Inventor： Kyung Hoon Kim , Sun Ki Cho
CPC classification number: G11C8/18 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/12
Abstract: A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.
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Patent Agency Ranking
公开(公告)号：US09773530B1
公开(公告)日：2017-09-26
申请号：US15232196
申请日：2016-08-09
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho
CPC classification number: G11C7/1066 , G11C7/1084 , G11C7/109 , G11C7/1093 , G11C7/225 , G11C11/4093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C2029/4402
Abstract: A semiconductor device may be provided. The semiconductor device may be configured to adjust a level of a first strobe signal to a predetermined level during a first time period. The semiconductor device may be configured to adjust a swing width of the first strobe signal during a second time period.
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7.发明授权公开(公告)号：US09124252B2
公开(公告)日：2015-09-01
申请号：US14581357
申请日：2014-12-23
Applicant: SK hynix Inc.
Inventor： Sung Woo Han , Ic Su Oh , Jun Ho Lee , Boo Ho Jung , Sun Ki Cho , Yang Hee Kim , Tae Hoon Kim
CPC classification number: H03K3/013 , G06F17/5022 , H03K5/12
Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.
Abstract translation: 提供了一种半导体装置，其包括多个输出缓冲器，其被配置为连接多个电源;以及数据噪声测量单元，被配置为将所述多个输出缓冲器中的所选输出缓冲器的输出数据固定为具有特定电平， 使用电容测量输出数据的噪声，并基于噪声控制多个输出缓冲器的转换速率。
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公开(公告)号：US12095465B2
公开(公告)日：2024-09-17
申请号：US17899030
申请日：2022-08-30
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Yang Ho Sur , Ic Su Oh
CPC classification number: H03K5/01 , H03K2005/00078
Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.
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公开(公告)号：US10305500B1
公开(公告)日：2019-05-28
申请号：US16038835
申请日：2018-07-18
Applicant: SK hynix Inc.
Inventor： Hae Kang Jung , Sun Ki Cho , Yong Suk Choi
Abstract: An amplification circuit is provided. The amplification circuit may include an amplification stage configured to amplify a first signal and a second signal, and generate third and fourth signals while in a first operation period. The amplification circuit may include a latch stage configured to latch the third and fourth signals while in a in a second operation period. The amplification circuit may supply a low voltage to the amplification stage during the first operation period, the low voltage to the latch stage during the second operation period, a high voltage to the amplification stage during the first operation period, and the high voltage to the latch stage during the second operation period.
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公开(公告)号：US09859892B2
公开(公告)日：2018-01-02
申请号：US15047864
申请日：2016-02-19
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho
IPC: H03K3/01 , H03K19/0185
CPC classification number: H03K19/018521
Abstract: A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.
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