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    MEMORY MODULE AND OPERATION METHOD OF THE SAME
    21.
    发明申请
    MEMORY MODULE AND OPERATION METHOD OF THE SAME 审中-公开

    公开(公告)号：US20190188162A1

    公开(公告)日：2019-06-20

    申请号：US16203591

    申请日：2018-11-28

    Applicant: SK hynix Inc.

    Inventor： Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin ,  Seung-Gyu Jeong

    IPC: G06F13/16 ,  G06F3/06

    Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

    Memory system and operating method thereof
    23.
    发明授权
    Memory system and operating method thereof 有权

    公开(公告)号：US10818365B2

    公开(公告)日：2020-10-27

    申请号：US16124927

    申请日：2018-09-07

    Applicant: SK hynix Inc.

    Inventor： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

    Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

    Memory system
    26.
    发明授权
    Memory system 有权

    公开(公告)号：US10559354B2

    公开(公告)日：2020-02-11

    申请号：US16007538

    申请日：2018-06-13

    Applicant: SK hynix Inc.

    Inventor： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin

    IPC: G11C8/10 ,  G11C13/00

    Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.

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