公开(公告)号：US20250140602A1

公开(公告)日：2025-05-01

申请号：US18837681

申请日：2023-01-31

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Hugo Biard

IPC: H01L21/762 ,  C30B29/36

Abstract: A method of manufacturing a composite structure including a thin layer of a first monocrystalline material arranged on a carrier substrate, the method including: providing an initial substrate of a second polycrystalline material; and depositing, by spin coating, at least on one front surface of the initial substrate, a layer of polymer resin including preformed 3D carbon-carbon bonds; performing a first annealing step at a temperature between 120° C. and 180° C. on the initial substrate provided with the polymer resin layer, to form a layer of cross-linked polymer resin; and performing a second annealing step at a temperature greater than 600° C., in a neutral atmosphere, to convert the layer of cross-linked polymer resin into a glassy carbon film. a composite structure includes a thin layer of a first monocrystalline material on a carrier substrate, which includes a glassy carbon film on an initial substrate of a second polycrystalline.

公开(公告)号：US12087631B2

公开(公告)日：2024-09-10

申请号：US17757797

申请日：2020-12-15

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/18 ,  H01L21/324 ,  H01L23/544 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/7806 ,  H01L21/02027 ,  H01L21/187 ,  H01L21/3247 ,  H01L23/544 ,  H01L29/1608 ,  H01L29/20 ,  H01L2223/54426

Abstract: A method for producing a composite structure comprises providing a donor substrate including a single-crystal material, and a support substrate having a first alignment pattern on a face or edge of the support substrate. A heat treatment is applied at least to the donor substrate to bring about a surface reorganization on at least one face of the donor substrate. The surface reorganization results in formation of first steps of nanometric amplitude, which are parallel to a first main axis. The donor substrate and the support substrate are optically aligned, to better than ±0.1° between a locating mark indicating the first main axis on the donor substrate and at least one alignment pattern of the support substrate. The donor substrate and the support substrate are then assembled together, and a thin layer is transferred from the donor substrate onto the support substrate.

公开(公告)号：US20240266172A1

公开(公告)日：2024-08-08

申请号：US18004594

申请日：2021-06-08

Applicant: Commissariat À L'énergie Atomique Et Aux Énergies Alternatives ,  Soitec

Inventor： Frédéric Allibert ,  Didier Landru ,  Oleg Kononchuk ,  Eric Guiot ,  Gweltaz Gaudin ,  Julie Widiez ,  Franck Fournel

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/04 ,  H01L21/324 ,  H01L23/00

CPC classification number: H01L21/187 ,  H01L21/02016 ,  H01L21/0485 ,  H01L21/324 ,  H01L24/83 ,  H01L2224/83894 ,  H01L2224/83948 ,  H01L2924/10253 ,  H01L2924/10272

Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).

公开(公告)号：US20240145294A1

公开(公告)日：2024-05-02

申请号：US18548616

申请日：2022-03-03

Applicant: Soitec

Inventor： Hugo Biard ,  Gweltaz Gaudin

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/02444 ,  H01L21/02529

Abstract: A method for manufacturing a semiconductor structure comprises: a) providing a temporary substrate comprising a material having a coefficient of thermal expansion close to that of silicon carbide; b) forming an intermediate graphite layer on a front face of the temporary substrate; c) depositing, on the intermediate layer, a polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns, d) transferring a useful monocrystalline silicon carbide layer onto the support layer in order to form a composite structure, the transfer using molecular adhesion bonding, e) forming an active layer on the useful layer, and f) disassembling, at an interface of or inside the intermediate layer, to structure to form the semiconductor structure including the active layer, the useful layer and the support layer. A composite structure is obtained by the method.

公开(公告)号：US20240030061A1

公开(公告)日：2024-01-25

申请号：US18255574

申请日：2021-11-19

Applicant: Commissariat À L'énergie Atomique Et Aux Énergies Alternatives ,  Soitec

Inventor： Larry Vincent ,  Shay Reboh ,  Lucie Le Van-Jodin ,  Frédéric Milesi ,  Ludovic Ecarnot ,  Gweltaz Gaudin ,  Didier Landru

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/76254 ,  H01L21/02019 ,  H01L21/30604 ,  H01L21/76218

Abstract: A donor substrate for transferring a single-crystal thin layer made of a first material, onto a receiver substrate. The donor substrate comprises: —a buried weakened plane delimiting an upper portion and a lower portion of the donor substrate, —in the upper portion, a first layer, a second layer adjacent to the buried weakened plane, and a stop layer between the first layer and the second layer the first layer composed of the first material, the stop layer being formed of a second material, —an amorphized sub-portion, made amorphous by ion implantation, having a thickness less than that of the upper portion, and including at least the first layer; the second layer comprising at least one single-crystal sub-layer, adjacent to the buried weakened plane. Two embodiments of a method may be used for transferring a single-crystal thin layer from the donor substrate.

公开(公告)号：US20230230868A1

公开(公告)日：2023-07-20

申请号：US18001033

申请日：2021-04-26

Applicant: Soitec

Inventor： Hugo Biard ,  Gweltaz Gaudin ,  Séverin Rouchier ,  Didier Landru

IPC: H01L21/683 ,  H01L21/324 ,  H01L21/322 ,  H01L21/18

CPC classification number: H01L21/6835 ,  H01L21/324 ,  H01L21/3221 ,  H01L21/187 ,  H01L2221/68381 ,  H01L2221/68368

Abstract: A temporary substrate, which is detachable at a detachment temperature higher than 1000° C. comprises:



a semiconductor working layer extending along a main plane,
a carrier substrate,
an intermediate layer having a thickness less than 20 nm arranged between the working layer and the carrier substrate,
a bonding interface located in or adjacent the intermediate layer,
gaseous atomic species distributed according to a concentration profile along the axis normal to the main plane, the atoms remaining trapped in the intermediate layer and/or in an adjacent layer of the carrier substrate with a thickness less than or equal to 10 nm and/or in an adjacent sublayer of the working layer with a thickness less than or equal to 10 nm when the temporary substrate is subjected to a temperature lower than the detachment temperature.

公开(公告)号：US09117686B2

公开(公告)日：2015-08-25

申请号：US14334370

申请日：2014-07-17

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/30 ,  H01L29/06 ,  H01L21/20 ,  H01L21/762 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  B81C3/00

CPC classification number: H01L29/0657 ,  B81C3/001 ,  B81C2203/036 ,  H01L21/2007 ,  H01L21/76251 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/2781 ,  H01L2224/27848 ,  H01L2224/279 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83014 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2224/27 ,  H01L21/78 ,  H01L2924/00

Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.

Abstract translation: 本发明涉及一种用于组装第一元件的方法，该第一元件包括至少一个第一晶片，衬底或至少一个芯片，以及至少一个第二晶片或衬底的第二元件，涉及形成表面层，称为 在每个衬底上，至少一个结合层在小于或等于300℃的温度下形成; 在组装之前至少部分地至少等于随后的接合界面强化温度但低于450℃的温度进行称为脱气退火的第一退火（称为脱气退火）。 通过与接合层的暴露表面接触而形成基板的组装，并且在接合界面强化温度低于450℃下进行组装结构的退火。

公开(公告)号：US20140327113A1

公开(公告)日：2014-11-06

申请号：US14334370

申请日：2014-07-17

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L29/06 ,  H01L23/00

CPC classification number: H01L29/0657 ,  B81C3/001 ,  B81C2203/036 ,  H01L21/2007 ,  H01L21/76251 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/2781 ,  H01L2224/27848 ,  H01L2224/279 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83014 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2224/27 ,  H01L21/78 ,  H01L2924/00

Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.

Abstract translation: 本发明涉及一种用于组装第一元件的方法，该第一元件包括至少一个第一晶片，衬底或至少一个芯片，以及至少一个第二晶片或衬底的第二元件，涉及形成表面层，称为 在每个衬底上，至少一个结合层在小于或等于300℃的温度下形成; 在组装之前至少部分地至少等于随后的接合界面强化温度但低于450℃的温度进行称为脱气退火的第一退火（称为脱气退火）。 通过与接合层的暴露表面接触而形成基板的组装，并且在接合界面强化温度低于450℃下进行组装结构的退火。

公开(公告)号：US08735946B2

公开(公告)日：2014-05-27

申请号：US14027528

申请日：2013-09-16

Applicant: Soitec

Inventor： Mohamad A Shaheen ,  Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure

IPC: H01L27/148

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

Abstract translation: 本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。 本发明还涉及制造这种基材的方法。

公开(公告)号：US20240030033A1

公开(公告)日：2024-01-25

申请号：US18257217

申请日：2021-11-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  SOITEC

Inventor： Gweltaz Gaudin ,  Ionut Radu ,  Franck Fournel ,  Julie Widiez ,  Didier Landru

IPC: H01L21/18 ,  H01L21/762 ,  H01L21/02 ,  H01L21/322

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/02002 ,  H01L21/3221

Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.