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公开(公告)号:US20220359420A1
公开(公告)日:2022-11-10
申请号:US17314916
申请日:2021-05-07
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , SeongHwan Park , JinHee Jung
Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.
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公开(公告)号:US20220270983A1
公开(公告)日:2022-08-25
申请号:US17662977
申请日:2022-05-11
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: Dong Won Son , Byeonghoon Kim , Sung Ho Choi , Sung Jae Lim , Jong Ho Shin , SungWon Cho , ChangOh Kim , KyoungHee Park
IPC: H01L23/552 , H01L23/31 , H01L23/00 , H01L23/498 , H01L23/367
Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
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公开(公告)号:US20220199545A1
公开(公告)日:2022-06-23
申请号:US17126621
申请日:2020-12-18
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , JinHee Jung , OMin Kwon , JiWon Lee , YuJeong Jang
IPC: H01L23/552 , H01L23/00 , H01L23/31 , H01L21/56 , H01L21/033
Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.
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公开(公告)号:US11342278B2
公开(公告)日:2022-05-24
申请号:US17008997
申请日:2020-09-01
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: SungWon Cho , ChangOh Kim , Il Kwon Shim , InSang Yoon , KyoungHee Park
IPC: H01L23/34 , H01L23/28 , H01L21/00 , H05K7/20 , H01L23/552 , H01L23/00 , H01L23/36 , H01L23/522 , H01L23/50 , H01L23/60 , H01L23/498 , H01L27/02 , H01L23/31 , H01L23/367
Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
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公开(公告)号:US20210335724A1
公开(公告)日:2021-10-28
申请号:US17369654
申请日:2021-07-07
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , KyoWang Koo , SungWon Cho
IPC: H01L23/552 , H01L23/31 , H01L23/04 , H01L25/065 , H01L21/78 , H01L25/00 , H01L21/56
Abstract: A semiconductor device has a substrate. A lid is disposed over the substrate. An encapsulant is deposited over the substrate. A film mask is disposed over the encapsulant with the lid exposed from the film mask and encapsulant. A conductive layer is formed over the film mask, encapsulant, and lid. The film mask is removed after forming the conductive layer.
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公开(公告)号:US20200075502A1
公开(公告)日:2020-03-05
申请号:US16116485
申请日:2018-08-29
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , KyoWang Koo , SungWon Cho
IPC: H01L23/552 , H01L23/31 , H01L23/04 , H01L21/56 , H01L21/78 , H01L25/00 , H01L25/065
Abstract: A semiconductor device has a substrate. A lid is disposed over the substrate. An encapsulant is deposited over the substrate. A film mask is disposed over the encapsulant with the lid exposed from the film mask and encapsulant. A conductive layer is formed over the film mask, encapsulant, and lid. The film mask is removed after forming the conductive layer.
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27.
公开(公告)号:US20170162495A1
公开(公告)日:2017-06-08
申请号:US15433866
申请日:2017-02-15
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: MinKyung Kang , YoungDal Roh , Dong Ju Jeon , KyoungHee Park
IPC: H01L23/498 , H01L23/00 , H01L21/48
CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2924/3841
Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
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公开(公告)号:US12136759B2
公开(公告)日:2024-11-05
申请号:US17452855
申请日:2021-10-29
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: HunTeak Lee , KyoungHee Park , KyungHwan Kim , SeungHyun Lee , SangJun Park
IPC: H05K1/18 , H01L21/56 , H01L23/31 , H01L23/36 , H01L23/552 , H01Q1/22 , H05K3/34 , H01L23/498 , H01L25/16 , H01R12/71
Abstract: A semiconductor device has a PCB with an antenna and a semiconductor package mounted onto the PCB. An epoxy molding compound bump is formed or disposed over the PCB opposite the semiconductor package. A first shielding layer is formed over the PCB. A second shielding layer is formed over the semiconductor package. A board-to-board (B2B) connector is disposed on the PCB or as part of the semiconductor package. A conductive bump is disposed between the semiconductor package and PCB.
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公开(公告)号:US20240113038A1
公开(公告)日:2024-04-04
申请号:US18511428
申请日:2023-11-16
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , SeongHwan Park , JinHee Jung
CPC classification number: H01L23/552 , H01L21/486 , H01L21/56 , H01L23/31 , H01L23/66 , H01Q1/2283
Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.
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公开(公告)号:US20230207485A1
公开(公告)日:2023-06-29
申请号:US18174790
申请日:2023-02-27
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: ChangOh Kim , KyoungHee Park , JinHee Jung , OMin Kwon , JiWon Lee , YuJeong Jang
IPC: H01L23/552 , H01L23/00 , H01L21/56 , H01L21/033 , H01L23/31
CPC classification number: H01L23/552 , H01L24/13 , H01L21/565 , H01L21/0334 , H01L23/3107 , H01L2924/15313
Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.
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