公开(公告)号：US10593612B2

公开(公告)日：2020-03-17

申请号：US15925420

申请日：2018-03-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina Somma ,  Fulvio Vittorio Fontana

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

公开(公告)号：US10211140B2

公开(公告)日：2019-02-19

申请号：US15616009

申请日：2017-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US20180053710A1

公开(公告)日：2018-02-22

申请号：US15797464

申请日：2017-10-30

Applicant: STMicroelectronics S.R.L.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/97 ,  H01L2021/6027 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

公开(公告)号：US20170271254A1

公开(公告)日：2017-09-21

申请号：US15616009

申请日：2017-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US20170250128A1

公开(公告)日：2017-08-31

申请号：US15282619

申请日：2016-09-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/495 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L28/60 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.

公开(公告)号：US20170200669A1

公开(公告)日：2017-07-13

申请号：US15470494

申请日：2017-03-27

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/4951 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49579 ,  H01L23/49805 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012

Abstract: A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.

公开(公告)号：US09704794B2

公开(公告)日：2017-07-11

申请号：US14733209

申请日：2015-06-08

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/06 ,  H01L23/04 ,  H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US09698027B2

公开(公告)日：2017-07-04

申请号：US15076754

申请日：2016-03-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: H01L21/00 ,  H01L23/495 ,  H05K7/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/4832 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method may include providing an electrically conductive laminar base member having a die attachment portion and a lead frame portion, producing a distribution of holes opening at a front surface of the base member, attaching an integrated circuit onto the front surface of the base member at the attachment portion, and producing a wire bonding pattern between the integrated circuit and wire bonding locations on the front surface of the base member at the lead frame portion. An electrically insulating package molding compound may be molded onto the front surface of the base member so that the integrated circuit and the wire bonding pattern are embedded in the package molding compound which penetrates into the holes opening at the front surface of the base member. The base member may be selectively etched from its back surface to produce residual portions of the base member at the wire bonding locations.

公开(公告)号：US20170125173A1

公开(公告)日：2017-05-04

申请号：US15164702

申请日：2016-05-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giovanni Scurati ,  Marco Morelli ,  Fulvio Vittorio Fontana

IPC: H01G11/18 ,  H01G11/52 ,  H01G11/78 ,  H01G11/22

CPC classification number: H01G11/18 ,  H01G11/08 ,  H01G11/14 ,  H01G11/22 ,  H01G11/52 ,  H01G11/78 ,  H01G11/82 ,  Y02E60/13

Abstract: A supercapacitor including: a shell; a chamber in the shell; a first electrode and a second electrode on respective walls of the chamber; and a separator arranged between the first electrode and the second electrode through the chamber. The separator includes a first perforated membrane and a second perforated membrane, which is movable with respect to the first membrane between a first position, in which the first membrane and the second membrane are separate and a second position, in which the first membrane and the second membrane are in contact and coupled for rendering the separator impermeable.

公开(公告)号：US12211772B2

公开(公告)日：2025-01-28

申请号：US17688013

申请日：2022-03-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Fulvio Vittorio Fontana ,  Davide Maria Benelli ,  Jefferson Sismundo Talledo

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.