公开(公告)号：US10672689B2

公开(公告)日：2020-06-02

申请号：US16460704

申请日：2019-07-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Frederick Ray Gomez ,  Tito Mangaoang, Jr. ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/60 ,  H01L23/31 ,  H01L23/00 ,  H01L21/66

Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.

公开(公告)号：US20190326201A1

公开(公告)日：2019-10-24

申请号：US16460704

申请日：2019-07-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Frederick Ray GOMEZ ,  Tito Mangaoang, JR. ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/60 ,  H01L21/48

Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.

公开(公告)号：US10347569B2

公开(公告)日：2019-07-09

申请号：US15801022

申请日：2017-11-01

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.

公开(公告)号：US20190043790A1

公开(公告)日：2019-02-07

申请号：US16154538

申请日：2018-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US10147673B2

公开(公告)日：2018-12-04

申请号：US15281800

申请日：2016-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/495 ,  H01L21/48

Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.

公开(公告)号：US20180130767A1

公开(公告)日：2018-05-10

申请号：US15863079

申请日：2018-01-05

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L24/85 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49544 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00015

Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.

公开(公告)号：US20180096923A1

公开(公告)日：2018-04-05

申请号：US15281800

申请日：2016-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49805 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49558 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.

公开(公告)号：US09818675B2

公开(公告)日：2017-11-14

申请号：US14674069

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49562 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.

公开(公告)号：US20160293450A1

公开(公告)日：2016-10-06

申请号：US14672664

申请日：2015-03-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Godfrey DIMAYUGA ,  Jefferson Talledo

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

Abstract translation: 半导体器件可以包括具有下导电层，介电层和上导电层的堆叠关系的多层互连板。 电介质层可以具有形成有从底部向上延伸的底部和倾斜侧壁的凹部。 上导电层可以包括跨过倾斜侧壁延伸的上导电迹线，并且下导电层可以包括下导电迹线。 半导体器件可以包括在下导电层和上导电层之间延伸的通孔，由凹槽中的多层互连板承载的IC，将上导电迹线耦合到IC的接合线以及邻近IC的封装材料以及与IC的相邻部分 多层互连板。

公开(公告)号：US20160190031A1

公开(公告)日：2016-06-30

申请号：US14582581

申请日：2014-12-24

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Godfrey Dimayuga

IPC: H01L23/36

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.

Abstract translation: 一个或多个实施例涉及具有一个或多个悬臂垫的半导体封装。 在一个实施例中，凹部位于面向悬臂垫的封装的衬底中。 悬臂焊盘包括形成有导电球的导电焊盘。 悬臂垫被配置成吸收作用在包装上的应力。