公开(公告)号：US20150097212A1

公开(公告)日：2015-04-09

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre MORIN ,  Qing LIU ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7842

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

Abstract translation: 一种用于形成半导体器件的方法包括在应力半导体绝缘体晶片的应力半导体层上形成掩模层。 形成包围应力半导体层的隔离沟槽。 隔离沟槽延伸穿过掩模层并穿过SOI晶片的氧化物层。 绝缘体形成在隔离沟槽中。 在电介质体和应力半导体层的相邻侧壁上形成松弛减小衬垫。 应力半导体层上的掩模层被去除。

公开(公告)号：US20200161299A1

公开(公告)日：2020-05-21

申请号：US16751036

申请日：2020-01-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  Prasanna KHARE ,  Nicolas LOUBET

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L21/84

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20180182902A1

公开(公告)日：2018-06-28

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01H49/00 ,  B82B3/00 ,  H01H1/00 ,  H01H59/00 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US20160293756A1

公开(公告)日：2016-10-06

申请号：US14675298

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/785

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract translation: 使用FinFET器件架构，在硅中实现隧道晶体管。 隧道FinFET具有非平面的垂直结构，其从形成在硅衬底中的掺杂漏极的表面延伸出来。 垂直结构包括由减法蚀刻工艺限定的轻掺杂的鳍，以及通过外延生长形成在鳍的顶部上的重掺杂源。 漏极和沟道具有相似的极性，与源极相反。 栅极邻接通道区域，电容地控制从相对侧通过通道的电流。 源极，漏极和栅极端子都可以通过在器件完成之后形成的前侧触点电可访问。 隧道FinFET的制造与常规CMOS制造工艺兼容，包括替换金属栅极和自对准接触工艺。 与传统的平面器件相比，低功耗操作允许隧道FinFET提供高电流密度。

公开(公告)号：US20160293371A1

公开(公告)日：2016-10-06

申请号：US14675359

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01H59/00 ,  H01H11/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US20160190325A1

公开(公告)日：2016-06-30

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing LIU ,  Nicholas LOUBET ,  Chun-chen YEH ,  Ruilong XIE ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

Abstract translation: 用于外延FinFET的锥形源极和漏极触点可防止接触处理期间FinFET的短路和损坏，从而提高器件的可靠性。 本发明的触头具有锥形侧壁和与源极和漏极区域中的翅片电接触的基座。 底座还为翅片提供了更大的接触面积，它们通过延伸部分增加。 凸起的隔离区域围绕翅片限定一个谷。 在源极/漏极接触形成期间，谷物衬有也覆盖翅片本身的共形屏障。 当形成接触时，屏障保护底层局部氧化物和相邻隔离区域免受气刨。 该谷填充有非晶硅层，其保护外延翅片材料免于接触形成期间的损坏。 栅极接触使用简单的锥形结构。

公开(公告)号：US20160043177A1

公开(公告)日：2016-02-11

申请号：US14456272

申请日：2014-08-11

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Tenko YAMASHITA ,  Chun-chen YEH ,  Veeraraghavan S. BASKER

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/1037 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract translation: 制造半导体器件的方法可以包括在绝缘层上形成半导体层之上的虚拟栅极，在半导体层上方形成侧壁间隔，在虚设栅极的相对侧上，在侧壁间隔物的相对侧上形成源极和漏极区域 并且在侧壁间隔物之间​​移除半导体层的虚拟栅极和下面的部分，以提供厚度小于稀薄沟道区域外的半导体层的剩余部分的薄化沟道区域。 该方法还可以包括在稀疏的沟道区域和侧壁间隔物之间​​形成替代栅极堆叠，并且具有在侧壁间隔物的相邻底部的水平面下方延伸的下部。

公开(公告)号：US20150333086A1

公开(公告)日：2015-11-19

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

公开(公告)号：US20160380118A1

公开(公告)日：2016-12-29

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01L21/306 ,  H01L21/02 ,  H01H49/00 ,  H01H59/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到其静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

公开(公告)号：US20160190322A1

公开(公告)日：2016-06-30

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/02 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在竖直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。