公开(公告)号：US20160190207A1

公开(公告)日：2016-06-30

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

Abstract translation: 提供了包括用于磁阻随机存取存储器（MRAM）的磁性隧道结（MTJ）和用于制造这种集成电路的方法的集成电路。 在一个示例中，制造集成电路的方法包括在金属互连上形成下电极。 金属互连设置在半导体衬底之上并且与基本上垂直于半导体衬底的法线对准。 下电极包括导电金属插头。 在与正常轴对准的下电极上形成MTJ堆叠。

公开(公告)号：US09129986B2

公开(公告)日：2015-09-08

申请号：US13929923

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract translation: 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US09853117B2

公开(公告)日：2017-12-26

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09691971B2

公开(公告)日：2017-06-27

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

公开(公告)号：US09613958B2

公开(公告)日：2017-04-04

申请号：US14735984

申请日：2015-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20170077259A1

公开(公告)日：2017-03-16

申请号：US15363563

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US20170077099A1

公开(公告)日：2017-03-16

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20150340491A1

公开(公告)日：2015-11-26

申请号：US14814183

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract translation: 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US09105559B2

公开(公告)日：2015-08-11

申请号：US14028517

申请日：2013-09-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Nathaniel Berliner ,  Hyun-Jin Cho ,  Johnathan Faltermeier ,  Kam-Leung Lee ,  Tenko Yamashita

IPC: H01L21/00 ,  H01L21/18 ,  H01L21/225

CPC classification number: H01L21/18 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/845 ,  H01L29/66803

Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

Abstract translation: 在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。 在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。 在第二示例性实施例中，NFET鳍和PFET鳍之一可以被第一掺杂剂组合物覆盖，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，接着进行退火以在两种掺杂剂中驱动。

公开(公告)号：US20150001627A1

公开(公告)日：2015-01-01

申请号：US13929923

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.