公开(公告)号：US11227860B2

公开(公告)日：2022-01-18

申请号：US16942854

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.

公开(公告)号：US20210375347A1

公开(公告)日：2021-12-02

申请号：US17196183

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin JO ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

IPC: G11C11/4072 ,  G11C11/4099 ,  G11C11/4093 ,  G11C5/06

Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

公开(公告)号：US11163453B2

公开(公告)日：2021-11-02

申请号：US17027978

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

IPC: G06F3/06 ,  G06N3/08 ,  G06F12/02

Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20210124527A1

公开(公告)日：2021-04-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G05D1/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US10236065B2

公开(公告)日：2019-03-19

申请号：US16049863

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

公开(公告)号：US10008272B2

公开(公告)日：2018-06-26

申请号：US15587461

申请日：2017-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee-Woong Kang ,  Donghun Kwak ,  Daeseok Byeon ,  Ju Seok Lee

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3445

Abstract: A nonvolatile memory system includes a nonvolatile memory device and a memory controller that controls the nonvolatile memory device. The nonvolatile memory device includes multiple memory blocks. Each of the memory blocks includes memory cells. Each of the memory cells has any one of an erase state and one of multiple different program states. An operation method of the nonvolatile memory system includes receiving a physical erase command from an external device. The operation method also includes performing a fast erase operation, responsive to the received physical erase command, with respect to at least one memory block so that first memory cells of the at least one memory block have a fast erase state different from the erase state.

公开(公告)号：US12211830B2

公开(公告)日：2025-01-28

申请号：US18179056

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L25/18 ,  H01L29/40

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US12205643B2

公开(公告)日：2025-01-21

申请号：US18407399

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Pansuk Kwak ,  Daeseok Byeon

IPC: G11C7/24 ,  G11C5/06 ,  G11C13/00 ,  G11C16/10

Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

公开(公告)号：US20240363172A1

公开(公告)日：2024-10-31

申请号：US18509021

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjeong Heo ,  Jaehue Shin ,  Daeseok Byeon ,  Yongsung Cho

IPC: G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a plurality of tri-state latches, a sensing node circuit configured to electrically couple a sensing node therein to a bitline of the memory device, a transfer node circuit configured to electrically couple a transfer node therein to the plurality of tri-state latches, and a node connection circuit configured to electrically connect the transfer node to the sensing node. In addition, the transfer node circuit and the node connection circuit are collectively configured to simultaneously reflect data stored in at least two of the plurality of tri-state latches to the sensing node, in response to a dump sequence operation.

公开(公告)号：US20240258180A1

公开(公告)日：2024-08-01

申请号：US18518114

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehong Kwon ,  Daeseok Byeon

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L22/30 ,  H01L23/481 ,  H01L23/528 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, wherein a type of the second semiconductor chip is different from a type of the first semiconductor chip; and a crack detection circuit including: a first crack detection line repeatedly passing through an interface between the first semiconductor chip and the second semiconductor chip; a second crack detection line including a bonding pad or a through-via structure contacting a surface of the second semiconductor chip opposite to the interface; and a crack detector in the second semiconductor chip, the crack detector being configured to output a first test signal to the first crack detection line, receive a first reception signal from the first crack detection line, output a second test signal to the second crack detection line, and receive a second reception signal from the second crack detection line.