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公开(公告)号：US20210028919A1
公开(公告)日：2021-01-28
申请号：US17070577
申请日：2020-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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公开(公告)号：US20190214976A1
公开(公告)日：2019-07-11
申请号：US16019070
申请日：2018-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wanghua Wu , Chih-Wei Yao
Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.
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23.发明授权公开(公告)号：US09746832B1
公开(公告)日：2017-08-29
申请号：US15432578
申请日：2017-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chih-Wei Yao
CPC classification number: G04F10/005 , H03M1/00 , H03M1/12 , H03M1/145 , H03M1/38 , H03M1/50 , H03M7/30 , H03M2201/4233
Abstract: An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V1 and a second voltage V2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V1 and the second voltage V2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V1, the second voltage V2 and the zero-crossing time, wherein V1 is a first negative voltage before the zero-crossing time, and V2 is a first positive voltage after the zero-crossing time.
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24.发明申请公开(公告)号：US20210313995A1
公开(公告)日：2021-10-07
申请号：US17354545
申请日：2021-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongrong ZUO , Chih-Wei Yao , Wanghua Wu
IPC: H03L7/099 , H03K17/687 , H04L7/033 , H01L29/78
Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.
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公开(公告)号：US10996634B2
公开(公告)日：2021-05-04
申请号：US16040963
申请日：2018-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chih-Wei Yao , Ronghua Ni
Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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Patent Agency Ranking
公开(公告)号：US20200186323A1
公开(公告)日：2020-06-11
申请号：US16274114
申请日：2019-02-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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公开(公告)号：US20180302069A1
公开(公告)日：2018-10-18
申请号：US15636387
申请日：2017-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing-Fai Loke , Chih-Wei Yao
CPC classification number: H03K5/06 , H02M3/07 , H03K5/24 , H03K2005/00019
Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.
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公开(公告)号：US09595915B2
公开(公告)日：2017-03-14
申请号：US15167040
申请日：2016-05-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai Loke , Chih-Wei Yao , Sunghwan Kim
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1243 , H03J2200/10
Abstract: Methods, apparatuses, and systems for providing a variable output using an array of cells are discussed. In the fine tuning bank of an apparatus, control is implemented by selecting a boundary cell from the array of cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.
Abstract translation: 讨论了使用单元阵列提供可变输出的方法，装置和系统。 在设备的微调库中，通过从单元阵列中选择边界单元并且使电路中的边界单元之前的每个单元接地并且在边界单元之后具有边界单元和边界单元之后的每个单元，来实现控制 电路路径连接到电压源。 电路路径可以是在微调库中使用温度计编码形成的路径。
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29.发明授权公开(公告)号：US09379662B2
公开(公告)日：2016-06-28
申请号：US14593251
申请日：2015-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai Loke , Chih-Wei Yao
CPC classification number: H03B5/04 , H03B5/1215 , H03B5/1237 , H03B5/1243 , H03B2201/0208
Abstract: A system using temperature tracking for a controlled oscillator (CO) is provided. The system includes at least one coarse tuning capacitor circuit including a plurality of selectable coarse tuning capacitors operable in at least three modes of operation, thereby allowing switching between each coarse capacitor of the plurality of selectable coarse capacitors when a selected coarse tuning capacitor has reached one of its high tuning range and low tuning range.
Abstract translation: 提供了一种使用受控振荡器（CO）温度跟踪的系统。 该系统包括至少一个粗调谐电容器电路，其包括可在至少三种工作模式下操作的多个可选择的粗调谐电容器，从而允许当所选择的粗调谐电容器达到一个时，在多个可选粗略电容器的每个粗电容器之间切换 的高调谐范围和低调谐范围。
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30.发明授权Communication system with frequency synthesis mechanism and method of operation thereof 有权具有频率合成机制的通信系统及其操作方法公开(公告)号：US09240914B2
公开(公告)日：2016-01-19
申请号：US14152617
申请日：2014-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chih-Wei Yao
CPC classification number: H04L27/0014 , H04L2027/0016 , H04L2027/0069
Abstract: A communication system includes: a frequency synthesizer, configured to reference a radio frequency (RF) signal, in a device including: a ring oscillator with track-and-hold circuit electrically connected to a reference clock, a bank of comparators, electrically connected to the ring oscillator with track-and-hold circuit, configured to measure a coarse timing, and an analog-to-digital converter, electrically connected to the ring oscillator with track-and-hold circuit, configured to generate a fine timing; a communication interface, electrically connected to the frequency synthesizer, is configured to receive a device transmission; and a control unit, electrically connected to the communication interface, is configured to display a receiver data from the a radio frequency (RF) signal.
Abstract translation: 通信系统包括：频率合成器，被配置为在包括以下的装置中参考射频（RF）信号：包括电路连接到参考时钟的跟踪和保持电路的环形振荡器，一组比较器，电连接到 具有跟踪保持电路的环形振荡器，被配置为测量粗略定时;以及模拟 - 数字转换器，电连接到具有跟踪和保持电路的环形振荡器，被配置为产生精细定时; 电连接到频率合成器的通信接口被配置为接收设备传输; 电连接到通信接口的控制单元被配置为从射频（RF）信号显示接收机数据。
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