公开(公告)号：US11336266B2

公开(公告)日：2022-05-17

申请号：US17222033

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Shin ,  Kyungtae Kang ,  Junha Lee ,  Tongsung Kim ,  Jangwoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: H03K3/017 ,  H03K19/21 ,  H03K5/24

Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.

公开(公告)号：US11315614B2

公开(公告)日：2022-04-26

申请号：US17150307

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon Na ,  Jeongdon Ihm ,  Jangwoo Lee ,  Byunghoon Jeong

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10

Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

公开(公告)号：US11199975B2

公开(公告)日：2021-12-14

申请号：US16861802

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon Na ,  Jangwoo Lee ,  Jeongdon Ihm

IPC: G06F13/00 ,  G06F3/06

Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

公开(公告)号：US09767873B2

公开(公告)日：2017-09-19

申请号：US15198564

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G06F11/10 ,  G11C16/32

CPC classification number: G11C7/22 ,  G06F11/10 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/32

Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

公开(公告)号：US09601171B2

公开(公告)日：2017-03-21

申请号：US14665148

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C16/06 ,  G11C16/32

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C16/06 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller.

公开(公告)号：US20140185389A1

公开(公告)日：2014-07-03

申请号：US14143154

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC: G11C7/10

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

公开(公告)号：US20250166693A1

公开(公告)日：2025-05-22

申请号：US18781150

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Jung ,  Changyoung Lee ,  Jeongdon Ihm

IPC: G11C11/408 ,  H01L23/00 ,  H03K19/20

Abstract: A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.

公开(公告)号：US20250078906A1

公开(公告)日：2025-03-06

申请号：US18818007

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

公开(公告)号：US12190995B2

公开(公告)日：2025-01-07

申请号：US18455904

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Jeong ,  Kyungtae Kang ,  Jangwoo Lee ,  Jeongdon Ihm

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42 ,  H03K19/173

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US12149247B2

公开(公告)日：2024-11-19

申请号：US17932023

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yoo-Chang Sung ,  Jeongdon Ihm ,  Hojun Chang ,  Jinseok Heo

IPC: H03K21/02 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40 ,  G11C7/10 ,  G11C7/22

Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.