公开(公告)号：US20220293730A1

公开(公告)日：2022-09-15

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Hyojin KIM ,  Haejun YU ,  Seunghun LEE ,  Kyungin CHOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

公开(公告)号：US20250089236A1

公开(公告)日：2025-03-13

申请号：US18954927

申请日：2024-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Youngjun KIM ,  Jinbum KIM

IPC: H10B12/00

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20240266350A1

公开(公告)日：2024-08-08

申请号：US18458447

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a lower structure; a barrier layer on the lower structure; and an upper structure on the barrier layer, wherein the lower structure includes lower source/drain regions; lower active layers spaced apart from each other, between the lower source/drain regions; and a lower gate structure and including portions below each of the lower active layers, wherein the upper structure includes upper source/drain regions and vertically overlapping the lower source/drain regions; upper active layers spaced apart from each other, between the upper source/drain regions, and vertically overlapping the lower active layers; and an upper gate structure, including portions on each of the upper active layers, and vertically overlapping the lower gate structure, and wherein the uppermost lower active layer of the lower active layers and the lowermost upper active layer of the upper active layers are in contact with the barrier layer.

公开(公告)号：US20240038842A1

公开(公告)日：2024-02-01

申请号：US18119037

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbin CHUN ,  Gyeom KIM ,  Dahye KIM ,  Youngkwang KIM ,  Jinbum KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

公开(公告)号：US20240006503A1

公开(公告)日：2024-01-04

申请号：US18128417

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Dahye KIM ,  Kyungbin CHUN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0673

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.

公开(公告)号：US20230268441A1

公开(公告)日：2023-08-24

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823431 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20230268395A1

公开(公告)日：2023-08-24

申请号：US18062713

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Sujin JUNG ,  Gyeom KIM ,  Dahye KIM ,  Ingyu JANG ,  Kyungbin CHUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.

公开(公告)号：US20210367083A1

公开(公告)日：2021-11-25

申请号：US17396059

申请日：2021-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye KIM ,  Dongchan SUH ,  Jinbum KIM

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US20210043763A1

公开(公告)日：2021-02-11

申请号：US16866628

申请日：2020-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee JUNG ,  Jinbum KIM ,  Dongil BAE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.