公开(公告)号：US20210183777A1

公开(公告)日：2021-06-17

申请号：US17090502

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo KIM ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/31

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US10651224B2

公开(公告)日：2020-05-12

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US12261157B2

公开(公告)日：2025-03-25

申请号：US18372846

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

公开(公告)号：US11948873B2

公开(公告)日：2024-04-02

申请号：US17555583

申请日：2021-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyun Lee ,  Dongwook Kim ,  Hwan Pil Park ,  Jongbo Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/16 ,  H01L23/31 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13001 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/1301 ,  H01L2224/13016 ,  H01L2224/1302 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13563 ,  H01L2225/1058

Abstract: A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

公开(公告)号：US20230352411A1

公开(公告)日：2023-11-02

申请号：US18090856

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Choi ,  Jongbo Shim ,  Heeyoub Kang ,  Sungeun Jo

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/12 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/538 ,  H01L25/16 ,  H01L23/12 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L23/3157 ,  H01L2223/6672 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/16237

Abstract: A semiconductor package includes a package substrate with first and second mounting regions at a top surface of the package substrate, a first semiconductor chip disposed on the first mounting region, a second semiconductor chip disposed on the second mounting region, an interposer substrate disposed on the second mounting region and covering the second semiconductor chip, a plurality of conductive connectors extending from a bottom surface of the interposer substrate to the top surface of the package substrate and laterally spaced apart from the second semiconductor chip, and a third semiconductor chip on a top surface of the interposer substrate. A first distance between a top surface of the first semiconductor chip and the top surface of the package substrate is greater than a second distance between the top surface of the interposer substrate and the top surface of the package substrate.

公开(公告)号：US11728230B2

公开(公告)日：2023-08-15

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Dongho Kim ,  Jin-Woo Park ,  Jongbo Shim

IPC: H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L21/4853 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

公开(公告)号：US11437293B2

公开(公告)日：2022-09-06

申请号：US16928159

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Jongbo Shim ,  Hwanpil Park ,  Jangwoo Lee

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

公开(公告)号：US11367714B2

公开(公告)日：2022-06-21

申请号：US16845567

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangwoo Lee ,  Jongbo Shim ,  Ji Hwang Kim ,  Yungcheol Kong ,  Youngbae Kim ,  Taehwan Kim ,  Hyunglak Ma

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373

Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

公开(公告)号：US20220013464A1

公开(公告)日：2022-01-13

申请号：US17150232

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US11152416B2

公开(公告)日：2021-10-19

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-Uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.