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公开(公告)号：US20230363143A1
公开(公告)日：2023-11-09
申请号：US18182539
申请日：2023-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiseok LEE , Moonyoung JEONG , Keunnam KIM , Seokhan PARK
CPC classification number: H10B12/315 , H10B12/482 , H10B12/05 , H10B80/00
Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.
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公开(公告)号：US20230262961A1
公开(公告)日：2023-08-17
申请号：US17957242
申请日：2022-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chan-Sic YOON , Kiseok LEE
IPC: H01L27/108
CPC classification number: H01L27/10823 , H01L27/10876
Abstract: A semiconductor device includes a substrate having an active region and a gate structure crossing the active region. The gate structure may include a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.
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公开(公告)号：US20210043629A1
公开(公告)日：2021-02-11
申请号：US16880230
申请日：2020-05-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hui-Jung KIM , Taehyun AN , Kiseok LEE , Keunnam KIM , Yoosang HWANG
IPC: H01L27/108 , G11C5/06
Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.
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公开(公告)号：US20200027734A1
公开(公告)日：2020-01-23
申请号：US16460468
申请日：2019-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hui-jung KIM , Kiseok LEE , Keunnam KIM , Yoosang HWANG
IPC: H01L21/02 , H01L21/306 , H01L27/108 , H01L27/22 , H01L27/24
Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer.
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公开(公告)号：US20190103407A1
公开(公告)日：2019-04-04
申请号：US16038052
申请日：2018-07-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiyoung KIM , Kiseok LEE , Bong-Soo KIM , Junsoo KIM , Dongsoo WOO , Kyupil LEE , HyeongSun HONG , Yoosang HWANG
IPC: H01L27/108
CPC classification number: H01L27/10805 , H01L27/0688 , H01L27/1085 , H01L28/86
Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.
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Patent Agency Ranking
公开(公告)号：US20180331046A1
公开(公告)日：2018-11-15
申请号：US16026937
申请日：2018-07-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiseok LEE , Sooho SHIN , Juik LEE , Jun Ho LEE , Kwangmin KIM , Ilyoung MOON , Jemin PARK , Bumseok SEO , Chan-Sic YOON , Hoin LEE
IPC: H01L23/544 , H01L27/108
CPC classification number: H01L23/544 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US20170181115A1
公开(公告)日：2017-06-22
申请号：US15206732
申请日：2016-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Jung KIM , Kiseok LEE
Abstract: A technique for sensor network, Machine to Machine (M2M), Machine Type Communication (MTC), Internet of Things (IoT) is provided. The present disclosure can be applied to intelligent services (smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail, security and safety service) based on the technique. A method for operating a user equipment (UE) is provided. The method includes receiving a first signal comprising a first category identification (ID) and a first unique ID from a first beacon device, determining a distance from the first beacon device based on the first signal, if the distance is below a threshold, registering the first category ID, and if a second signal comprising the registered first category ID from a second beacon device, displaying information corresponding to a second unique ID of the second signal.
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公开(公告)号：US20250040129A1
公开(公告)日：2025-01-30
申请号：US18655731
申请日：2024-05-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungbo KO , Inwoo KIM , Jongmin KIM , Kiseok LEE , Minyoung LEE , Seongtak CHO , Inho CHA
IPC: H10B12/00
Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.
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公开(公告)号：US20240341081A1
公开(公告)日：2024-10-10
申请号：US18388295
申请日：2023-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hongjun LEE , Keunnam KIM , Seungmuk KIM , Kiseok LEE
CPC classification number: H10B12/315 , G11C5/063 , H10B12/482 , H10B12/485 , H10B12/488 , H10B12/50
Abstract: A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.
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公开(公告)号：US20240284657A1
公开(公告)日：2024-08-22
申请号：US18529698
申请日：2023-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minho CHOI , Kiseok LEE , Chansic YOON , Chulkwon PARK , Jaybok CHOI
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/315 , H10B12/482
Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.
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