公开(公告)号：US12112071B2

公开(公告)日：2024-10-08

申请号：US18217063

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0613 ,  G06F3/0679 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US12047082B2

公开(公告)日：2024-07-23

申请号：US17994296

申请日：2022-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/22 ,  H03K5/133 ,  H03L7/081 ,  H03L7/085 ,  G11C29/02

CPC classification number: H03L7/0816 ,  G11C7/222 ,  H03K5/133 ,  H03L7/085 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

公开(公告)号：US11921664B2

公开(公告)日：2024-03-05

申请号：US18077406

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06F13/40 ,  G06F18/214

CPC classification number: G06F13/4072 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0679 ,  G06F18/214

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：US11475955B2

公开(公告)日：2022-10-18

申请号：US17393784

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha Lee ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C16/06 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US20220101894A1

公开(公告)日：2022-03-31

申请号：US17410210

申请日：2021-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Chiweon Yoon ,  Byunghoon Jeong ,  Youngmin Jo

IPC: G11C7/10 ,  H01L25/065

Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

公开(公告)号：US11217283B2

公开(公告)日：2022-01-04

申请号：US17012845

申请日：2020-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha Lee ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US09886379B2

公开(公告)日：2018-02-06

申请号：US14668015

申请日：2015-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Kitae Park ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G06F12/02 ,  G11C16/10 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F13/1673 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/1072 ,  G11C16/102

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.