公开(公告)号：US20180102151A1

公开(公告)日：2018-04-12

申请号：US15723532

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G11C7/22 ,  G06F13/16 ,  G06F1/12 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US09754650B2

公开(公告)日：2017-09-05

申请号：US15187967

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Tae-Young Oh

IPC: G11C7/22 ,  G11C7/12

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/12 ,  G11C2207/2254

Abstract: A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.

公开(公告)号：US09754649B2

公开(公告)日：2017-09-05

申请号：US15180175

申请日：2016-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C7/22 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G06F3/06 ,  G11C7/10

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US12300353B2

公开(公告)日：2025-05-13

申请号：US18238232

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

公开(公告)号：US11081152B2

公开(公告)日：2021-08-03

申请号：US16874916

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10706953B2

公开(公告)日：2020-07-07

申请号：US16215752

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Jin Cho ,  Tae-Young Oh ,  Jung-Hwan Park

IPC: G11C29/44 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/52

Abstract: A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.

公开(公告)号：US10607660B2

公开(公告)日：2020-03-31

申请号：US15959344

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwa Kim ,  Tae-Young Oh ,  Jin-Hoon Jang ,  Seok-Jin Cho

IPC: G11C5/14 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4096

Abstract: A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode.

公开(公告)号：US10579263B2

公开(公告)日：2020-03-03

申请号：US16169178

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US09898438B2

公开(公告)日：2018-02-20

申请号：US14879618

申请日：2015-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Tae-Young Oh

IPC: G06F3/06 ,  G06F13/42

CPC classification number: G06F13/4243

Abstract: A memory system includes a transmitter and a receiver. The transmitter is configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface. The data burst includes a first data and a subsequent data. The receiver is configured to receive the data signal, to detect the first symbol lock pattern based on the received data signal, and to find the first data of the data burst according to the detected first symbol lock pattern.

公开(公告)号：US09767050B2

公开(公告)日：2017-09-19

申请号：US15065211

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-Yeon Doo ,  Tae-Young Oh ,  Kwang-Il Park

IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406

CPC classification number: G06F13/1636 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.