公开(公告)号：US07982530B2

公开(公告)日：2011-07-19

申请号：US12494437

申请日：2009-06-30

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: G05F1/10

CPC classification number: H02M3/073 ,  G11C5/145 ,  H02M2001/0022 ,  H02M2003/077

Abstract: The internal voltage generating apparatus includes a first charge pumping circuit, an external voltage level detector, and a second charge pumping circuit. The first charge pumping circuit outputs an internal voltage and selectively performs first charge pumping for the internal voltage depending on a result detecting a level of the internal voltage feed-backed. The external voltage level detector detects a level of an external voltage and outputs the result detecting the level of the internal voltage and outputs a result detecting the level of the external voltage as a detection signal. The second charge pumping circuit performs second charge pumping for the internal voltage together with the first charge pumping against a case in which the level of the external voltage is lower than a predetermined level by the detection signal of the external voltage level detector.

Abstract translation: 内部电压产生装置包括第一电荷泵浦电路，外部电压电平检测器和第二电荷泵浦电路。 第一电荷泵浦电路输出内部电压，并且根据检测到提供的内部电压的电平的结果选择性地对内部电压进行第一次充电泵浦。 外部电压电平检测器检测外部电压的电平，并输出检测内部电压的电平的结果，并输出检测外部电压电平的结果作为检测信号。 第二电荷泵浦电路通过外部电压电平检测器的检测信号，对外部电压的电平低于预定电平的情况，对内部电压和第一电荷泵浦进行第二电荷泵浦。

公开(公告)号：US07800424B2

公开(公告)日：2010-09-21

申请号：US11958277

申请日：2007-12-17

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: G06F1/04

CPC classification number: G11C7/08 ,  G11C5/143 ,  G11C5/145 ,  G11C11/4091

Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

Abstract translation: 一种用于在存储装置中提供过驱动信号的装置。 该装置包括：电压检测块，其根据外部电压的电平输出多个检测信号;以及脉冲发生器，其根据多个检测信号输出具有不同脉冲宽度的过驱动信号。

公开(公告)号：US07773432B2

公开(公告)日：2010-08-10

申请号：US12118810

申请日：2008-05-12

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/06 ,  G11C7/08 ,  G11C2207/065

Abstract: A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage.

Abstract translation: 本发明提供一种具有驱动器的半导体存储器件，该驱动器被配置为顺序执行过驱动和正常驱动操作。 该半导体存储器件包括：驱动器，其输出驱动信号，该驱动信号用具有高于正常驱动电压的电压电平的过驱动电压驱动驱动信号，然后随后以正常驱动电压驱动驱动信号 。 半导体存储器件还包括驱动电压调节器，其检测过驱动电压的电平并且响应于检测到的过驱动电压的水平来补偿正常驱动电压的电压电平的变化。

公开(公告)号：US08369122B2

公开(公告)日：2013-02-05

申请号：US12838332

申请日：2010-07-16

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC classification number: H03L7/00

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US08279702B2

公开(公告)日：2012-10-02

申请号：US12840966

申请日：2010-07-21

Applicant: Jae Bum Ko ,  Sang Jin Byeon

Inventor： Jae Bum Ko ,  Sang Jin Byeon

IPC: G11C8/00

CPC classification number: H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract translation: 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

公开(公告)号：US20120057413A1

公开(公告)日：2012-03-08

申请号：US12948874

申请日：2010-11-18

Applicant: Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

Inventor： Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

IPC: G11C8/18 ,  G11C29/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C29/006 ,  G11C29/023

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract translation: 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

公开(公告)号：US20110074471A1

公开(公告)日：2011-03-31

申请号：US12651018

申请日：2009-12-31

Applicant: Sin Hyun JIN ,  Sang Jin Byeon

Inventor： Sin Hyun JIN ,  Sang Jin Byeon

IPC: H03L7/00

CPC classification number: H03K17/22 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。

公开(公告)号：US09928205B2

公开(公告)日：2018-03-27

申请号：US13162702

申请日：2011-06-17

Applicant: Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

Inventor： Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

IPC: G06F13/42 ,  G11C16/20 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC classification number: G06F13/4247

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

公开(公告)号：US09257975B2

公开(公告)日：2016-02-09

申请号：US13445761

申请日：2012-04-12

Applicant: Sang Jin Byeon ,  Tae Sik Yun

Inventor： Sang Jin Byeon ,  Tae Sik Yun

IPC: G06F1/00 ,  H03K5/06 ,  G06F1/12 ,  H03K5/08

CPC classification number: H03K5/06 ,  G06F1/12 ,  H03K5/08

Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

Abstract translation: 提供一种半导体装置。 该装置包括：传输控制单元，被配置为响应于具有第一脉冲宽度的接收脉冲信号，生成具有大于第一脉冲宽度的第二脉冲宽度的传输控制信号和具有大于第一脉冲宽度的第三脉冲宽度的同步控制信号 第二脉冲宽度。 该装置还包括：接收控制单元，被配置为响应于同步控制信号产生接收控制信号。

公开(公告)号：US09252129B2

公开(公告)日：2016-02-02

申请号：US13602257

申请日：2012-09-03

Applicant: Tae Sik Yun ,  Sang Jin Byeon

Inventor： Tae Sik Yun ,  Sang Jin Byeon

IPC: H03K19/00 ,  H01L25/065 ,  H03K19/003 ,  G01R31/28

CPC classification number: H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract translation: 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于 控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 以及通过垂直形成的从芯片的第二通芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。