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    Ultra high throughput wafer vacuum processing system
    21.
    发明授权
    Ultra high throughput wafer vacuum processing system 失效
    超高产量晶圆真空处理系统

    公开(公告)号：US5855681A

    公开(公告)日：1999-01-05

    申请号：US751485

    申请日：1996-11-18

    申请人： Dan Maydan ,  Sasson Somekh ,  Ashok Sinha ,  Kevin Fairbairn ,  Christopher Lane ,  Kelly Colborne ,  Hari K. Ponnekanti ,  W. N.(Nick) Taylor

    发明人： Dan Maydan ,  Sasson Somekh ,  Ashok Sinha ,  Kevin Fairbairn ,  Christopher Lane ,  Kelly Colborne ,  Hari K. Ponnekanti ,  W. N.(Nick) Taylor

    IPC分类号： H01L21/00 ,  H01L21/205 ,  H01L21/677 ,  H01L21/687 ,  C23C16/00 ,  C23F1/02

    CPC分类号： H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/68707 ,  H01L21/68785

    摘要： The present invention generally provides a cassette-to-cassette vacuum processing system which concurrently processes multiple wafers and combines the advantages of single wafer process chambers and multiple wafer handling for high quality wafer processing, high wafer throughput and reduced footprint. In accordance with one aspect of the invention, the system is preferably a staged vacuum system which generally includes a loadlock chamber for introducing wafers into the system and which also provides wafer cooling following processing, a transfer chamber for housing a wafer handler, and one or more processing chambers each having two or more processing regions which are isolatable from each other and preferably share a common gas supply and a common exhaust pump. The processing regions also preferably include separate gas distribution assemblies and RF power sources to provide a uniform plasma density over a wafer surface in each processing region. The processing chambers are configured to allow multiple, isolated processes to be performed concurrently in at least two processing regions so that at least two wafers can be processed simultaneously in a chamber with a high degree of process control provided by shared gas sources, shared exhaust systems, separate gas distribution assemblies, separate RF power sources, and separate temperature control systems.

    摘要翻译： 本发明通常提供一种盒式到盒式真空处理系统，其同时处理多个晶片，并且结合了单晶片处理室和多个晶片处理的优点，用于高质量晶片处理，高晶圆吞吐量和减小的占地面积。 根据本发明的一个方面，该系统优选地是分级真空系统，其通常包括用于将晶片引入系统中并且还提供后续处理的晶片冷却的负载锁定室，用于容纳晶片处理器的传送室，以及一个或 更多的处理室具有可彼此隔离的两个或更多个处理区域，并且优选地共享公共气体供应源和公共排气泵。 处理区域还优选地包括单独的气体分配组件和RF功率源，以在每个处理区域中在晶片表面上提供均匀的等离子体密度。 处理室被配置为允许在至少两个处理区域中同时执行多个隔离过程，使得可以在室内同时处理至少两个晶片，具有由共用气源提供的高程度的过程控制，共用排气系统 ，独立的气体分配组件，独立的射频电源和独立的温度控制系统。

    Method of making electrostatic chuck with conformal insulator film
    22.
    发明授权
    Method of making electrostatic chuck with conformal insulator film 失效
    用保形绝缘膜制作静电卡盘的方法

    公开(公告)号：US5753132A

    公开(公告)日：1998-05-19

    申请号：US725482

    申请日：1996-10-04

    申请人： Shamouil Shamouilian ,  Sasson Somekh ,  Hyman J. Levinstein ,  Manoocher Birang ,  Semyon Sherstinsky ,  John F. Cameron

    发明人： Shamouil Shamouilian ,  Sasson Somekh ,  Hyman J. Levinstein ,  Manoocher Birang ,  Semyon Sherstinsky ,  John F. Cameron

    IPC分类号： B23Q3/15 ,  H01L21/683 ,  H02N13/00 ,  B44C1/22

    CPC分类号： H01L21/6831 ,  H01L21/6833 ,  H02N13/00

    摘要： A process for fabricating an electrostatic chuck (20) comprising the steps of (c) forming a base (80) having an upper surface with cooling grooves (85) therein, the grooves sized and distributed for holding a coolant therein for cooling the base; and (d) pressure conforming an electrical insulator layer (45) to the grooves on the base by the steps of (i) placing the base into a pressure forming apparatus (25) and applying an electrical insulator layer over the grooves in the base; and (ii) applying a sufficiently high pressure onto the insulator layer to pressure conform the insulator layer to the grooves to form a substantially continuous layer of electrical insulator conformal to the grooves on the base.

    摘要翻译： 一种用于制造静电卡盘（20）的方法，包括以下步骤：（c）形成具有上表面的基部（80），其中具有冷却槽（85），所述凹槽的尺寸和分布用于将冷却剂保持在其中用于冷却基座; 和（d）通过以下步骤将电绝缘体层（45）施加到基底上的凹槽上：（i）将基底放置在压力成形设备（25）中并将电绝缘体层施加在基底中的凹槽上; 和（ii）将足够高的压力施加到绝缘体层上以使绝缘体层压到沟槽上，以形成与基底上的凹槽保形的基本上连续的电绝缘层。

    Apparatus for cleaning a shield in a physical vapor deposition chamber
    23.
    发明授权
    Apparatus for cleaning a shield in a physical vapor deposition chamber 失效
    用于清洁物理气相沉积室中的屏蔽的装置

    公开(公告)号：US5294320A

    公开(公告)日：1994-03-15

    申请号：US878938

    申请日：1992-05-05

    申请人： Sasson Somekh ,  Dan Maydan

    发明人： Sasson Somekh ,  Dan Maydan

    IPC分类号： C23C14/22 ,  C23C14/56 ,  C23C14/34

    CPC分类号： H01J37/32862 ,  C23C14/22 ,  C23C14/564

    摘要： In a method for in situ cleaning a shield bearing of excess target material deposited in a physical vapor deposition chamber, during a cleaning cycle, a vacuum is created in the physical vapor deposition chamber. A gas mixture which includes a reactive gas is introduced into the physical vapor deposition chamber. The reactive gas is activated by plasma discharge. During the cleaning, the gas mixture is continuously removed from the vapor deposition chamber along with reaction products.

    摘要翻译： 在用于原位清洁沉积在物理气相沉积室中的过量目标材料的屏蔽轴承的方法中，在清洁循环期间，在物理气相沉积室中产生真空。 将包括反应气体的气体混合物引入物理气相沉积室。 反应气体通过等离子体放电激活。 在清洁过程中，气体混合物与反应产物一起从气相沉积室中连续除去。

    Variable thickness self-aligned photoresist process
    24.
    发明授权
    Variable thickness self-aligned photoresist process 失效
    可变厚度自对准光刻胶工艺

    公开(公告)号：US4231811A

    公开(公告)日：1980-11-04

    申请号：US75095

    申请日：1979-09-13

    申请人： Sasson Somekh ,  C. Norman Ahlquist

    发明人： Sasson Somekh ,  C. Norman Ahlquist

    IPC分类号： H01L21/027 ,  H01L21/266 ,  H01L21/336 ,  H01L21/26

    CPC分类号： H01L29/66575 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/266 ,  Y10S148/10 ,  Y10S148/137 ,  Y10S148/141 ,  Y10S438/948

    摘要： A process for forming with a single masking step regions of different thicknesses in a photo-sensitive layer is disclosed. A masking member or reticle includes opaque and transparent areas and areas with a grating. The pitch of the periodic grating is of a lesser dimension than can be resolved by the masking projection apparatus. The photo-sensitive region illuminated by the grating receives uniform illumination at an intermediate intensity, thereby providing, after developing, a layer with regions of intermediate thickness.

    摘要翻译： 公开了一种在光敏层中用不同厚度的单个掩模步骤形成区域的方法。 掩模构件或掩模版包括不透明区域和具有光栅的区域。 周期光栅的间距比由掩模投影装置可以解析的尺寸小。 由光栅照射的光敏区域以中等强度接收均匀的照明，从而在显影之后提供具有中等厚度的区域的层。

    Method of forming a damascene structure with integrated planar dielectric layers
    26.
    发明授权
    Method of forming a damascene structure with integrated planar dielectric layers 有权
    用集成平面介质层形成镶嵌结构的方法

    公开(公告)号：US07229907B2

    公开(公告)日：2007-06-12

    申请号：US10942302

    申请日：2004-09-15

    申请人： Tom Wu ,  Sasson Somekh ,  Chien Chiang

    发明人： Tom Wu ,  Sasson Somekh ,  Chien Chiang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  C25D3/02 ,  C25D3/38 ,  C25D5/22 ,  C25D5/34 ,  C25D7/123 ,  C25D17/001 ,  H01L21/3212 ,  H01L21/32125

    摘要： Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed portion of the substrate; depositing a conductive metal over the barrier metal, the deposited conductive metal having a thickness sufficient to fill the etched pattern; planarizing the conductive metal to form a planar metal layer; and polishing the metal layer and the barrier metal in a single polishing step using an abrasive-free polish until the dielectric material surrounding the pattern is exposed.

    摘要翻译： 提供了用于在工件基板上形成电路部件的方法。 该方法包括以下步骤：在衬底上沉积电介质材料; 蚀刻通过介电材料的图案以暴露基底的一部分; 在介电材料和基板的暴露部分上沉积阻挡金属; 在阻挡金属上沉积导电金属，沉积的导电金属具有足以填充蚀刻图案的厚度; 平面化导电金属以形成平坦的金属层; 并且在单次抛光步骤中使用无研磨抛光剂抛光金属层和阻挡金属，直到暴露图案周围的电介质材料。

    Method of forming a damascene structure with integrated planar dielectric layers
    27.
    发明申请
    Method of forming a damascene structure with integrated planar dielectric layers 有权
    用集成平面介质层形成镶嵌结构的方法

    公开(公告)号：US20060057829A1

    公开(公告)日：2006-03-16

    申请号：US10942302

    申请日：2004-09-15

    申请人： Tom Wu ,  Sasson Somekh ,  Chien Chiang

    发明人： Tom Wu ,  Sasson Somekh ,  Chien Chiang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/7684 ,  C25D3/02 ,  C25D3/38 ,  C25D5/22 ,  C25D5/34 ,  C25D7/123 ,  C25D17/001 ,  H01L21/3212 ,  H01L21/32125

    摘要： Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed portion of the substrate; depositing a conductive metal over the barrier metal, the deposited conductive metal having a thickness sufficient to fill the etched pattern; planarizing the conductive metal to form a planar metal layer; and polishing the metal layer and the barrier metal in a single polishing step using an abrasive-free polish until the dielectric material surrounding the pattern is exposed.

    摘要翻译： 提供了用于在工件基板上形成电路部件的方法。 该方法包括以下步骤：在衬底上沉积电介质材料; 蚀刻通过介电材料的图案以暴露基底的一部分; 在介电材料和基板的暴露部分上沉积阻挡金属; 在阻挡金属上沉积导电金属，沉积的导电金属具有足以填充蚀刻图案的厚度; 平面化导电金属以形成平坦的金属层; 并且在单次抛光步骤中使用无研磨抛光剂抛光金属层和阻挡金属，直到暴露图案周围的电介质材料。

    Carrier head with a substrate detection mechanism for a chemical mechanical polishing system
    29.
    发明授权
    Carrier head with a substrate detection mechanism for a chemical mechanical polishing system 有权

    公开(公告)号：US06343973B1

    公开(公告)日：2002-02-05

    申请号：US09595500

    申请日：2000-06-16

    申请人： Sasson Somekh

    发明人： Sasson Somekh

    IPC分类号： B24B4900

    CPC分类号： B24B37/30 ,  B24B37/0053

    摘要： A carrier head for a chemical mechanical polishing system includes a substrate sensing mechanism. The carrier head includes a base and a flexible member connected to the base to define a chamber. A lower surface of the flexible member provides a substrate receiving surface. The substrate sensing mechanism includes a sensor to measure a pressure in the chamber and generate an output signal representative thereof, and a processor configured to indicate whether the substrate is attached to the substrate receiving surface in response to the output signal.