公开(公告)号：US07889537B2

公开(公告)日：2011-02-15

申请号：US12118064

申请日：2008-05-09

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

公开(公告)号：US07602651B2

公开(公告)日：2009-10-13

申请号：US11953319

申请日：2007-12-10

申请人： Eiichi Makino ,  Shigeo Ohshima

发明人： Eiichi Makino ,  Shigeo Ohshima

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1063 ,  G11C2207/105

摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

摘要翻译： 本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘 具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

公开(公告)号：US20050036378A1

公开(公告)日：2005-02-17

申请号：US10948818

申请日：2004-09-23

申请人： Kazuaki Kawaguchi ,  Shigeo Ohshima

发明人： Kazuaki Kawaguchi ,  Shigeo Ohshima

IPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

摘要翻译： 在具有迟写功能的FCRAM中，当第一命令信号指示“写活动”时，是否要执行写操作或自动刷新操作是基于第二命令信号确定的。 例如，当第二命令信号指示“写入”时，通过后期写入方案执行存储器单元的写入操作。 当第二命令信号指示“自动刷新”时，执行自动刷新操作。 在紧接在该自动刷新操作之前的写入操作的最后写入周期中，预定用于选择作为自动刷新对象的存储单元的地址。 在最后一个写入周期内对存储单元的数据写入完成后，执行自动刷新的行预充电。 之后，对所选择的存储单元执行自动刷新操作（即，数据读取操作和数据恢复操作）。

公开(公告)号：US06636445B2

公开(公告)日：2003-10-21

申请号：US09736053

申请日：2000-12-13

申请人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

发明人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

IPC分类号： G11C700

CPC分类号： G11C7/1069 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/107

摘要： An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

摘要翻译： 用于锁存写入数据的输入数据寄存器被布置在存储器芯部分的存储单元阵列附近的位置。 输入数据寄存器布置在用于将数据写入存储单元的数据路径的上游侧。 将写入数据引脚的数据输入写入到下游侧的终端位置，经由数据输入缓冲器，串行/并行转换电路和写数据线被锁存在输入数据寄存器中。 锁存在输入数据寄存器中的数据在下一个写周期中通过DQ写驱动器，数据线对，I / O门和位线对写入存储单元。

公开(公告)号：US06313676B1

公开(公告)日：2001-11-06

申请号：US09527561

申请日：2000-03-16

申请人： Katsumi Abe ,  Masahiro Kamoshida ,  Shigeo Ohshima

发明人： Katsumi Abe ,  Masahiro Kamoshida ,  Shigeo Ohshima

IPC分类号： H03L706

CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03K5/135 ,  H03L7/0814 ,  H04L7/0037

摘要： A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.

摘要翻译： 半导体集成电路具有内部时钟信号发生器电路和数据输入/输出电路。 内部时钟信号发生器电路包括时钟接收器，同步延迟控制电路，时钟驱动器，输出控制电路，延迟监视器和控制信号发生器电路。 因此，在延迟测量模式中，基于测量开始信号和测量停止信号，在延迟监视器中设置输入信号的延迟。 在延迟测量模式完成之后，延迟监视器使得从时钟接收器输出的信号CLK延迟延迟测量模式中设置的延迟。 此外，延迟监视器将延迟的信号输出到同步延迟控制电路。

公开(公告)号：US06260128B1

公开(公告)日：2001-07-10

申请号：US09132438

申请日：1998-08-11

申请人： Shigeo Ohshima ,  Shinji Miyamoto

发明人： Shigeo Ohshima ,  Shinji Miyamoto

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/22

摘要： A clock signal is supplied to an input buffer circuit. A delay circuit has a delay time equal to a difference between the cycle time for latency (CL) of 3 and the cycle time for latency of 2. When CL=2, a transfer gate outputs a clock signal delayed by the delay circuit, as a clock signal CLK2. The clock signal CLK2 initiates the operation in the second stage at the latency of 3. The operation at the latency of 2 can, therefore, be performed in a cycle time having a sufficient margin, without increasing the speed of the operation in the second stage at the latency of 3.

摘要翻译： 时钟信号被提供给输入缓冲电路。 延迟电路具有等于3的等待时间（CL）的周期时间与等待时间2的周期时间之间的差的延迟时间。当CL = 2时，传输门输出延迟电路延迟的时钟信号，如 时钟信号CLK2。 时钟信号CLK2以等待时间3开始第二级的操作。因此，在等待时间为2的操作可以在具有足够余量的周期时间内执行，而不增加第二阶段中的操作速度 在3的延迟。

公开(公告)号：US5239509A

公开(公告)日：1993-08-24

申请号：US824356

申请日：1992-01-23

申请人： Tatsuo Ikawa ,  Shigeo Ohshima

发明人： Tatsuo Ikawa ,  Shigeo Ohshima

IPC分类号： B23F5/02 ,  B23F23/00 ,  B23F23/12 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/14 ,  G11C29/20 ,  G11C29/56

CPC分类号： G11C29/20 ,  G11C29/02 ,  G11C7/1075

摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit.

摘要翻译： 一种半导体存储器件，具有：用于随机访问存储单元阵列的RAM端口，所述存储单元阵列具有以矩阵形式布置的存储单元; 用于串行访问存储单元阵列的一行的数据的SAM端口; 模式切换单元，用于在外部接收模式切换信号时，将SAM端口的操作模式切换到普通数据输出模式和测试模式之间; 以及地址指针输出单元，用于当通过模式切换单元将操作模式切换到测试模式时，输出SAM端口的地址指针。

公开(公告)号：US5134455A

公开(公告)日：1992-07-28

申请号：US708993

申请日：1991-05-31

申请人： Katsuji Tokonami ,  Shigeo Ohshima

发明人： Katsuji Tokonami ,  Shigeo Ohshima

IPC分类号： H01L21/82 ,  H01L23/485 ,  H01L23/528

CPC分类号： H01L24/06 ,  H01L23/5286 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14

摘要： There is disclosed a semiconductor integrated circuit device comprising: an external input signal lead provided outside a semiconductor chip; a power supply lead provided outside the semiconductor chip; a first electrode connected to an internal circuit on the semiconductor chip, and arranged close to the external input signal lead, wherein when the circuit is caused to be operative, the first electrode is connected to the external input signal lead; and a second electrode connected to the first electrode on the semiconductor chip, and arranged close to said power supply lead, wherein when the circuit is not caused to be operative, the second electrode is connected to the power supply lead. This invention is applicable to the device wherein there are provided a plurality of internal circuits. In this case, a plurality of the first electrodes drawn out from the internal circuits are arranged close to the external input signal lead, and a plurality of the second electrodes similarly drawn out from the internal circuits are arranged close to the power supply lead.

公开(公告)号：US5084635A

公开(公告)日：1992-01-28

申请号：US588809

申请日：1990-09-27

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： H03K19/20 ,  G06F15/78 ,  G06F17/50 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1075 ,  G11C7/1015

摘要： A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

公开(公告)号：US5007028A

公开(公告)日：1991-04-09

申请号：US552851

申请日：1990-07-16

申请人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/1075

摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.