公开(公告)号：US07602651B2

公开(公告)日：2009-10-13

申请号：US11953319

申请日：2007-12-10

申请人： Eiichi Makino ,  Shigeo Ohshima

发明人： Eiichi Makino ,  Shigeo Ohshima

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1063 ,  G11C2207/105

摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

摘要翻译： 本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘 具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

公开(公告)号：US07732930B2

公开(公告)日：2010-06-08

申请号：US11851118

申请日：2007-09-06

申请人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

发明人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5385 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device including a circuit substrate including n number of terminals; a semiconductor chip provided on the circuit substrate and including n number of terminals; and a relay chip including a triangular substrate having a first side, a second side and a third side which form triangle, n number of first terminals located along the first side, n number of second terminals located along the second side, and a plurality of wires connecting the first terminals and the second terminals respectively; a first wire connecting each of the n number of terminals of the circuit substrate to a corresponding first terminal among the n number of first terminals; and a second wire connecting each of the n number of terminals of the semiconductor chip to a corresponding second terminal among the n number of second terminals.

摘要翻译： 一种半导体器件，包括：包括n个端子的电路基板; 设置在电路基板上并包括n个端子的半导体芯片; 以及包括三角形基板的中继芯片，所述三角基板具有形成三角形的第一侧面，第二侧面和第三侧面，沿着第一侧设置的n个第一端子，沿着第二侧设置的n个第二端子， 分别连接第一端子和第二端子的电线; 将所述电路基板的n个端子中的每一个连接到所述n个第一端子中的对应的第一端子的第一导线; 以及将n个半导体芯片的n个端子中的每一个连接到n个第二端子中的对应的第二端子的第二线。

公开(公告)号：US20080054491A1

公开(公告)日：2008-03-06

申请号：US11851118

申请日：2007-09-06

申请人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

发明人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

IPC分类号： H01L23/50 ,  H05K1/00 ,  H05K3/10

CPC分类号： H01L23/5385 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate. The plurality of third pads of the wiring chip are located along two adjacent sides of a wiring chip substrate of the wiring chip, and are connected to each other by a plurality of metal wires, sequentially from the third pads closest from a contact point of the two sides; The plurality of metal wires each include a first part drawn from each of the plurality of third pads located along a first side of the two sides inward the wiring chip so as to be parallel to, or so as to form an acute angle with, a second side of the two sides, a second part drawn from each of the plurality of third pads located along the second side inward the wiring chip so as to be parallel to, or so as to form an acute angle with, the first side, and a third part connecting the first part and the second part to each other in a straight manner. The plurality of metal wires are formed such that a wiring width of each metal wire, a wiring interval between each metal wire and a metal wire adjacent and outer thereto, and a wiring pitch which is a sum of each wiring width and a corresponding wiring interval are set so as to minimize a difference between wiring capacitances of each adjacent metal wires among the plurality of metal wires.

摘要翻译： 根据本发明的半导体器件包括其上包括多个第一焊盘的衬底; 至少一个半导体芯片，包括多个第二焊盘; 以及包括多个第三焊盘的至少一个布线芯片。 半导体芯片的多个第二焊盘的一部分电连接到布线芯片的多个第三焊盘的一部分，并且布线芯片的多个第三焊盘的另一部分电连接到 多个基片的第一垫片。 布线芯片的多个第三焊盘沿着布线芯片的布线芯片基板的两个相邻侧布置，并且从多个金属布线彼此连接，从最接近 双方; 多个金属线各自包括从沿着两侧的第一侧向内布置的多个第三焊盘中的每一个的第一部分，其与平行于或与之形成锐角的第一部分 所述两侧的第二侧，从所述多个第三焊盘中的每一个沿着所述第二侧向内布置在所述布线芯片上的第二部分，以与所述第一侧平行或与之形成锐角;以及 将第一部分和第二部分以直线方式彼此连接的第三部分。 多个金属线被形成为使得每个金属线的布线宽度，每个金属布线和与其外部的金属线之间的布线间隔以及布线间距是每个布线宽度和相应的布线间隔之和的布线间距 被设置为使多个金属线中的每个相邻的金属线的布线电容之间的差最小化。

公开(公告)号：US20070206399A1

公开(公告)日：2007-09-06

申请号：US11682478

申请日：2007-03-06

申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。

公开(公告)号：US5491430A

公开(公告)日：1996-02-13

申请号：US242714

申请日：1994-05-13

申请人： Eiichi Makino ,  Masaru Koyanagi

发明人： Eiichi Makino ,  Masaru Koyanagi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00361

摘要： The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

摘要翻译： 控制电压产生电路1输出的控制电压phi 1在外部电源电压Vcc低于晶体管P1的阈值的范围内处于低电平，但是当外部电源电压Vcc 上升。 在匹配外部电源电压Vcc之后，控制电压phi 1以与外部电源电压Vcc相同的方式增加。 通过使用具有如上所述的用于输出电路的特性的控制电压，受控的是低电压工作输出部分6的晶体管P4的栅极仅在低于预定值的电压下工作。 输出电路的全压工作输出部分5的晶体管P2总是基于数据输出控制电路3的控制信号phi H而工作。当外部电源电压低于预定值时，晶体管 P4完全打开，使其电导增加。 在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近的操作余量减小。

公开(公告)号：US20100271879A1

公开(公告)日：2010-10-28

申请号：US12754206

申请日：2010-04-05

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C16/04 ,  G11C5/14 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a common voltage generating circuit which maintains a fixed voltage supply capability, and a plurality of voltage generating circuits which are disposed in accordance with a number of the plurality of planes, and a control circuit configured to control the power supply voltage generating circuit.

摘要翻译： 半导体集成电路包括存储单元阵列，其包括多个平面，每个平面包括多个存储单元;电源电压产生电路，包括保持固定电压供应能力的公共电压发生电路;以及多个电压产生电路， 根据多个平面的数量设置，以及控制电路，其被配置为控制电源电压产生电路。

公开(公告)号：US07590027B2

公开(公告)日：2009-09-15

申请号：US11867443

申请日：2007-10-04

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C7/10

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays, a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays, a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal, and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal.

摘要翻译： 非易失性半导体器件包括多个字线，多个位线，多个存储单元阵列，具有连接到所述字线和所述位线的多个电可重新编程的存储器单元，数据程序控制部件，其编程 多个第一多位数据，每一个具有第一位数，或多个第二多位数据，每一个具有所述第一多位数据的第二位数的第二位数两倍于所述多个存储单元阵列; 存储从所述多个存储单元阵列中读取的每个所述字线的所述多个第一多位数据或所述多个第二多位数据的页缓冲器电路，传送所述多个第一多位数据 多位数据或所述多个第二多位数据，其从与所述第二时钟信号同步的所述页缓冲器电路中的每一个读取，具有周期wh 是第一时钟信号的两倍，以及从所述数据传送部分接收所述数据并与所述第一时钟信号同步地从外部输出所述数据的数据输出部分。

公开(公告)号：US20060236290A1

公开(公告)日：2006-10-19

申请号：US11107038

申请日：2005-04-15

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

摘要翻译： 用于布置平行导线以减小电容变化的系统和方法。 在一个实施例中，布置成线性阵列的多个第一部件通过对应的信号线耦合到该线性阵列的末端处的第二部件。 每个信号线具有垂直于线性阵列方向延伸的垂直部分和平行于线性阵列方向延伸的平行部分。 平行部分交错，使得更长的平行部分与更短的平行部分相邻，而不是简单地从最长到最短的布置。 在一个实施例中，平行部分的较长的一半在整个平行部分的长度上减小，而平行部分的较短的一半长度增加。 在另一个实施例中，连续更长/更短的平行部分是该系列的交替侧。

公开(公告)号：US06819737B2

公开(公告)日：2004-11-16

申请号：US10606249

申请日：2003-06-26

申请人： Tsutomu Suzuki ,  Hiroshi Takano ,  Eiichi Makino ,  Takaaki Kobiki ,  Akira Kurome

发明人： Tsutomu Suzuki ,  Hiroshi Takano ,  Eiichi Makino ,  Takaaki Kobiki ,  Akira Kurome

IPC分类号： H05G102

CPC分类号： A61B6/035 ,  A61B6/4488 ,  A61B6/56

摘要： An X-ray CT scanner having an X-ray tube for radiating X-rays to a subject, an X-ray detector for detecting X-rays that have penetrated the subject, a circular plate-like rotary member with an opening for insertion of a subject and having the X-ray tube and the X-ray detector mounted thereon at opposing positions with respect to the opening, a support for rotatably supporting the rotary member, and a rotary drive for rotating the rotary member around the subject. The X-ray tube and the X-ray detector are mounted on a side surface of the rotary member, the side surface being a unit mounting surface for mounting a control unit relating to at least one of generation and detection of the X-rays.

摘要翻译： 一种X射线CT扫描器，其具有用于向被检体照射X射线的X射线管，用于检测穿过被检体的X射线的X射线检测器，具有用于插入被检体的开口的圆板状旋转部件 被摄体，并且在相对于开口的相对位置安装有X射线管和X射线检测器，用于可旋转地支撑旋转部件的支撑件和用于使旋转部件绕着被检体旋转的旋转驱动器。 X射线管和X射线检测器安装在旋转构件的侧表面上，侧表面是用于安装与X射线的产生和检测中的至少一个有关的控制单元的单元安装表面。

公开(公告)号：US08284584B2

公开(公告)日：2012-10-09

申请号：US12426444

申请日：2009-04-20

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C5/06

CPC分类号： H01L27/101 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/24

摘要： A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and fourth part, each of the parts having a resistivity, the second part having a first resistivity, a different value of the first resistance being set for each of the plurality of first wires, the first, third and fourth parts having a second or third resistivity which is lower than the first resistivity, the first and second part being electrically connected in series by the first contact, the second and third part being electrically connected in series by the second contact, and the third and fourth part being electrically connected in series by the third contact.

摘要翻译： 半导体集成电路器件包括第一元件，第二元件，多个第一，第二和第三触点，以及多个具有多个第一布线的信号线，并且连接第一和第二元件，每个第一布线 具有第一，第二，第三和第四部分，每个部分具有电阻率，第二部分具有第一电阻率，为多个第一导线中的每一个设置第一电阻的不同值，第一，第三和第 第四部分具有低于第一电阻率的第二或第三电阻率，第一和第二部分通过第一接触串联电连接，第二和第三部分通过第二接触串联电连接，第三部分和第三部分 第四部分通过第三触点串联电连接。