公开(公告)号：US11175980B2

公开(公告)日：2021-11-16

申请号：US16729206

申请日：2019-12-27

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Darshana H. Mehta ,  Nicholas Lien

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/52 ,  G06F11/10

Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory region, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

公开(公告)号：US20210133025A1

公开(公告)日：2021-05-06

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  H03M13/11

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

公开(公告)号：US20210064249A1

公开(公告)日：2021-03-04

申请号：US16560858

申请日：2019-09-04

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Antoine Khoueir

IPC: G06F3/06 ,  G06F11/07

Abstract: Technologies are described herein for or extending the lifespan of a solid-state drive by using worn-out MLC flash blocks in SLC mode to extend their useful life. Upon identifying a first storage location in the storage media of an SSD as a candidate for defecting, the first storage location is switched from a first programming mode to a second programming mode, where the second programming mode results in a lower storage density of storage locations than the first programming mode. In conjunction with switching the first storage location to the first programming mode, a second storage location in the storage media is switched from the second programming mode to the first programming mode to ensure that the total capacity of the storage media remains at or above the rated capacity.

公开(公告)号：US20180366209A1

公开(公告)日：2018-12-20

申请号：US15625313

申请日：2017-06-16

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Antoine Khoueir ,  Ara Patapoutian

IPC: G11C29/10 ,  G11C29/30 ,  G11C29/42 ,  G06F12/02 ,  G06F3/06

Abstract: Systems and methods presented herein provide for monitoring block, page, and/or stripe degradation. In one embodiment, a controller is operable to scan a first block of memory to identify a failure in a portion of the first block. The controller suspends input/output (I/O) operations to the failed portion of the first block, and tests the failed portion of the first block to determine if the failure is a transient failure. Testing includes loading the portion of the first block with data, and reading the data from the loaded portion of the first block. If the failure subsides after testing, the controller is further operable to determine that the failure is a transient failure, and to resume I/O operations to the portion of the first block.

公开(公告)号：US12112821B2

公开(公告)日：2024-10-08

申请号：US17845643

申请日：2022-06-21

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C29/44 ,  G11C16/34 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C16/3495 ,  G11C29/1201 ,  G11C29/46

Abstract: A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

公开(公告)号：US11899590B2

公开(公告)日：2024-02-13

申请号：US17844141

申请日：2022-06-20

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/60

Abstract: A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

公开(公告)号：US11853213B2

公开(公告)日：2023-12-26

申请号：US17730920

申请日：2022-04-27

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2212/60

Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

公开(公告)号：US20220405003A1

公开(公告)日：2022-12-22

申请号：US17841083

申请日：2022-06-15

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06

Abstract: Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

公开(公告)号：US20220404982A1

公开(公告)日：2022-12-22

申请号：US17844174

申请日：2022-06-20

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06 ,  G11C29/08

Abstract: A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

公开(公告)号：US11513879B2

公开(公告)日：2022-11-29

申请号：US16427502

申请日：2019-05-31

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Antoine Khoueir

IPC: G06F11/00 ,  G06F11/07 ,  G11C16/14 ,  G11C16/34 ,  G11C16/26 ,  G06F11/10 ,  G11C16/04

Abstract: Weak erase detection and mitigation techniques are provided that detect permanent failures in solid-state storage devices. One exemplary method comprises obtaining an erase fail bits metric for a solid-state storage device; and detecting a permanent failure in at least a portion of the solid-state storage device causing weak erase failure mode by comparing the erase fail bit metric to a predefined fail bits threshold. In at least one embodiment, the method also comprises mitigating for the permanent failure causing the weak erase failure mode for one or more cells of the solid-state storage device. The mitigating for the permanent failure comprises, for example, changing a status of the one or more cells to a defective state and/or a retired state. The detection of the permanent failure causing the weak erase failure mode comprises, for example, detecting the weak erase failure mode without an erase failure.