SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

    公开(公告)号:US20220399355A1

    公开(公告)日:2022-12-15

    申请号:US17776342

    申请日:2020-11-24

    Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

    SEMICONDUCTOR DEVICE
    26.
    发明公开

    公开(公告)号:US20230284429A1

    公开(公告)日:2023-09-07

    申请号:US18016745

    申请日:2021-07-19

    CPC classification number: H10B12/00 G11C11/405 G11C11/54

    Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor. The output current is current flowing when the third transistor operates in a subthreshold region.

    Control Circuit Of Secondary Battery And Electronic Device

    公开(公告)号:US20230273637A1

    公开(公告)日:2023-08-31

    申请号:US18024198

    申请日:2021-08-25

    CPC classification number: G05F3/24 H01M10/425

    Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes. The third capacitor retains a voltage applied to the back gate by being applied with a voltage for polarization inversion in the ferroelectric layer.

    MEMORY DEVICE
    28.
    发明申请

    公开(公告)号:US20220262858A1

    公开(公告)日:2022-08-18

    申请号:US17629804

    申请日:2020-07-31

    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

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