公开(公告)号：US5130666A

公开(公告)日：1992-07-14

申请号：US662243

申请日：1991-02-27

申请人： Germano Nicollini

发明人： Germano Nicollini

IPC分类号： H03F3/347 ,  H03F1/08 ,  H03F3/30 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/086 ,  H03F3/3023 ,  H03F3/45659 ,  H03F2200/261

摘要： The preamplifier includes a first amplifier stage (M1A, M2A) and a second amplifier stage (M1, M2), both of which are of the differential type, have the same dimensions, have their output nodes connected in parallel to one another, and drive a load formed by a current mirror (M3, M4). A third differential amplifier stage with single-ended output (M6, M7, M8, M9, M10, M11) driven by the current mirror supplies the final output voltage of the preamplifier. The input nodes of the first stage act as input for the differential signal to be amplified, and the input nodes of the second stage are driven respectively by a preset reference voltage (V.sub.CM) and by a voltage (V.sub.x) which is proportional to the final output voltage of the preamplifier. A negative voltage-current feedback is thus obtained, due to the fact that a difference in current is generated between the respective output nodes of the first and second stages; the difference is proportional to the difference between the differential signal to be amplified and the difference between the reference voltage and the voltage which is proportional to the final output voltage (V.sub.x -V.sub.CM).

公开(公告)号：US4920510A

公开(公告)日：1990-04-24

申请号：US63258

申请日：1987-06-17

申请人： Daniel Senderowicz ,  Guido Torelli ,  Germano Nicollini

发明人： Daniel Senderowicz ,  Guido Torelli ,  Germano Nicollini

IPC分类号： H03H15/00 ,  H03H17/02

CPC分类号： H03H17/02

摘要： The sampled-data band-pass filter device is based on the phenomemon of aliasing, and allows the substantially unattenuated passage of the components of an input signal at a frequency included within an interval comprised between a first frequency (f.sub.sL) and a second frequency (f.sub.sH), arranged around a third frequency (f.sub.sO), while it substantially attenuates the components of the input signal at frequencies outside said interval, and furthermore automatically performs the shift to low-frequency, around a fourth frequency (f.sub.O), of the components of the input signal which have passed without attenuation. According to the invention, the device comprises, as filter element, a sampled-data band-pass filter which employs, as sampling frequency, a fifth frequency (f.sub.s) equal to a whole submultiple of a sixth frequency (nf.sub.s) equal to the sum of the third frequency (f.sub.sO) and the fourth frequency (f.sub.O), having, as lower and upper cutoff frequencies, respectively the difference between the sixth frequency and the second frequency (nf.sub.s -f.sub.sH) and the difference between the sixth frequency and the first frequency (nf.sub.s -f.sub.sL).

摘要翻译： 采样数据带通滤波器装置基于混叠的特征，并且允许以包括在第一频率（fsL）和第二频率（fsL）之间的间隔内的频率的输入信号的分量的基本上未衰减的通过 fsH），其大致在第三频率（fs0）周围的频率衰减输入信号的分量，并且还自动地执行向组件的第四频率（f0）附近的低频移位 通过没有衰减的输入信号。 根据本发明，该装置包括作为滤波器元件的采样数据带通滤波器，采样数据带通滤波器采用等于等于总和的第六频率（nfs）的整数倍的第五频率（fs）作为采样频率 具有分别为第六频率和第二频率（nfs-fsH）之间的差和第六频率与第一频率之间的差的第三频率（fs0）和第四频率（f0）分别为下限和上限截止频率 频率（nfs-fsL）。

公开(公告)号：US20140153746A1

公开(公告)日：2014-06-05

申请号：US14129320

申请日：2012-07-13

申请人： Germano Nicollini ,  Andrea Barbieri

发明人： Germano Nicollini ,  Andrea Barbieri

IPC分类号： H04R3/00

CPC分类号： H04R3/00 ,  H03F3/005 ,  H03F3/187 ,  H03F3/45475 ,  H03F3/45928 ,  H03F3/45937 ,  H03F3/45959 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45528

摘要： A microphone preamplifier circuit (60) is described, adapted to be connected to a microphone circuit (MCD), the microphone circuit (MCD) comprising a microphone (3) and at least one output node (MO, MO′). The microphone preamplifier circuit (60) comprises a preamplifier (PA) comprising: —at least one input node (10, 10′) adapted to be connected to said output node (MO, MO′); —an operational amplifier (OA) comprising at least one input (20, 20′) and at least one output (21, 21′); —at least one input DC decoupling capacitor (CD, CD′) connected between said input node (10, 10′) and said first input of the operational amplifier (20,20′); at least one feedback capacitor (C2A, C2A′) connected between the input (20,20′) and the output (21, 21′) of the operational amplifier (OA) in order to set together with said input DC decoupling capacitor (CD, CD′) a gain value of the preamplifier circuit (60); —a first (40, 40′) and a second feed node (41, 41′) adapted to be fed by a first (VCIMIN) and a second (VCM) bias voltage respectively. The preamplifier (PA) further comprises at least one switched capacitor (C2B, C2B′) adapted to be selectively and alternatively connected under the control of a clock signal (CK): —between said input (20, 20′) and said output (21, 21′) of the operational amplifier (OA); and—between said first (40, 40′) and said second (41, 41′) feed node.

摘要翻译： 麦克风前置放大器电路（60）被描述为适于连接到麦克风电路（MCD），麦克风电路（MCD）包括麦克风（3）和至少一个输出节点（MO，MO'）。 麦克风前置放大器电路（60）包括前置放大器（PA），包括： - 适于连接到所述输出节点（MO，MO'）的至少一个输入节点（10,10'）; - 运算放大器（OA），包括至少一个输入（20,20'）和至少一个输出（21,21'）; 连接在所述输入节点（10,10'）和所述运算放大器（20,20'）的所述第一输入端之间的至少一个输入DC去耦电容器（CD，CD'）; 连接在运算放大器（OA）的输入（20,20'）和输出（21,21'）之间的至少一个反馈电容器（C2A，C2A'），以便与所述输入DC去耦电容器 ，CD'）前置放大器电路（60）的增益值; - 第一（40,40'）和第二馈电节点（41,41'），分别适于由第一（VCIMIN）和第二（VCM）偏置电压馈送。 前置放大器（PA）还包括至少一个开关电容器（C2B，C2B'），其适于在时钟信号（CK）的控制下选择性地和可选地连接： - 在所述输入（20,20'）和所述输出（ 21，21'）; 并且在所述第一（40,40'）和所述第二（41,41'）馈送节点之间。

公开(公告)号：US20140035665A1

公开(公告)日：2014-02-06

申请号：US14002416

申请日：2012-02-27

申请人： Germano Nicollini ,  Carlo Pinna

发明人： Germano Nicollini ,  Carlo Pinna

IPC分类号： H03F3/45 ,  H03H11/12

CPC分类号： H03F3/45264 ,  H03F3/3028 ,  H03F3/45 ,  H03F3/4565 ,  H03F3/45663 ,  H03F2200/297 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/30021 ,  H03F2203/30081 ,  H03F2203/30114 ,  H03F2203/45311 ,  H03F2203/45626 ,  H03F2203/45648 ,  H03F2203/45674 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03H11/1213

摘要： The invention relates to a two stage class AB operational amplifier (200) for driving a load (L), comprising at least an input stage (201) comprising differential input terminals (IN+, IN−) and an output terminal (N) to provide a driving signal (VN). In addition, the operational amplifier comprises an output stage (202) comprising a first (A) and second (B) input terminals operatively associated to the input stage (201) to be driven on the basis of said driving signal (VN) and a driving circuit (203) operatively interposed between said input stage (201) and the output stage (202). The operational amplifier is characterised in that the driving circuit (203) comprises a first portion (204) comprising at least one resistor (R1) operatively connected between a first reference potential (Vcc) via a first circuitry block (MT, M11) comprising a PMOS transistor (MT) and a second reference potential (GND) via a second circuitry block (M12, MS) comprising a NMOS transistor (MS). The voltage drop (VR1) on said at least a first resistor (R1) is fixed to a value depending on said first (Vcc) and second (GND) reference potentials and the gate-source voltages of said PMOS (MT) and NMOS (MS) transistors, respectively. The driving circuit further comprises a second portion (205) comprising a first resistor (R2) and a second resistor (R2′) having first terminals connected one another in a common terminal (P) which is connected to the output terminal (N) of the input stage. Said first resistor (R2) has a second terminal connected the first input terminal (A) of the output stage and said second resistor (R2′) has a second terminal connected to the second input terminal (B) of the output stage. Said second terminals (A, B) of the first (R2) and second resistors (R2′) are connected to the first reference potential (Vcc) via a third circuitry block (MW, M9) and to the second reference potential (GND) via a fourth circuitry block (M10, MX), respectively. Said third (MW, M9) and fourth (M10, MX) circuitry blocks are arranged to be operatively connected to said first (MT, M11) and second (M12, MS) circuitry blocks, respectively, so that the voltage drop (VR2) between the second terminals (A, B) is substantially equal to the value of the voltage drop (VR1) across said at least one resistor (R1).

公开(公告)号：US08044718B2

公开(公告)日：2011-10-25

申请号：US12637091

申请日：2009-12-14

申请人： Germano Nicollini ,  Angelo Nagari

发明人： Germano Nicollini ,  Angelo Nagari

IPC分类号： H03F1/36

CPC分类号： H03G1/0088 ,  H03F3/45475 ,  H03F2203/45526 ,  H03F2203/45594 ,  H03H11/126 ,  H03H11/1291

摘要： An integrated programmable gain amplifier circuit that receives at an input an analog signal, circuit including an operational amplifier and a gain setup network comprising resistive elements and selection elements, which may be controlled in order to setup the gain of the amplifier circuit. The gain setup network further includes capacitive elements, for defining, together with the resistive elements and the operational amplifier, an anti-aliasing filter of the active RC type.

摘要翻译： 一种集成可编程增益放大器电路，其在输入端接收模拟信号，包括运算放大器的电路和包括电阻元件和选择元件的增益设置网络，其可被控制以便建立放大器电路的增益。 增益设置网络还包括用于与电阻元件和运算放大器一起定义主动RC型的抗混叠滤波器的电容元件。

公开(公告)号：US07864493B2

公开(公告)日：2011-01-04

申请号：US11943424

申请日：2007-11-20

申请人： Carlo Pinna ,  Germano Nicollini

发明人： Carlo Pinna ,  Germano Nicollini

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electric circuit includes a supply terminal to receive an outer supply voltage and a voltage regulator coupled to the supply terminal and to provide supply and resting voltages. A lock-out circuit is switchable between active and inactive states and receives the supply voltage at a supply node to generate, in the active state, an output voltage on a output terminal thereof. A protection circuit protects against electrostatic discharge, having at least one first diode coupled between the supply node and the output terminal. A cut-off electronic lock couples, in the inactive state, the supply node to the supply terminal by reverse biasing the at least one first diode to make a voltage of the output terminal float.

摘要翻译： 电路包括用于接收外部电源电压的电源端子和耦合到电源端子的电压调节器，并提供电源和静止电压。 锁定电路可在有源和非活动状态之间切换，并且在电源节点处接收电源电压，以在激活状态下产生其输出端上的输出电压。 保护电路防止静电放电，具有耦合在电源节点和输出端之间的至少一个第一二极管。 截止电子锁通过反向偏置所述至少一个第一二极管以使输出端子的电压浮动而将处于非活动状态的电源节点耦合到电源端子。

公开(公告)号：US07400285B2

公开(公告)日：2008-07-15

申请号：US11569630

申请日：2005-05-19

申请人： Germano Nicollini ,  Pierangelo Confalonieri ,  Riccardo Martignone

发明人： Germano Nicollini ,  Pierangelo Confalonieri ,  Riccardo Martignone

IPC分类号： H03M1/66

CPC分类号： H04B1/707

摘要： A circuit for reconstructing an analog signal starting from a digital input signal includes a digital to analog converter and a low pass-filter connected at the output of the converter for receiving the analog format signal and outputting a reconstructed analog signal. The low pass filter is an active filter continuous in time and current-coupled to the output of the digital-analog converter. The digital-analog converter is of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency of the analog signal.

摘要翻译： 用于重建从数字输入信号开始的模拟信号的电路包括数模转换器和连接在转换器输出端的低通滤波器，用于接收模拟格式信号并输出​​重构的模拟信号。 低通滤波器是时间上连续的有源滤波器，并且与数模转换器的输出电流耦合。 数模转换器是以大于模拟信号的奈奎斯特频率的采样频率工作的电流导向型。

公开(公告)号：US20070262894A1

公开(公告)日：2007-11-15

申请号：US11569630

申请日：2005-05-19

申请人： Germano Nicollini ,  Pierangelo Confalonieri ,  Riccardo Martignone

发明人： Germano Nicollini ,  Pierangelo Confalonieri ,  Riccardo Martignone

IPC分类号： H03M1/66 ,  H04M1/78

CPC分类号： H04B1/707

摘要： There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format;—a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

摘要翻译： 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换成模拟信号的数模转换器（DAC）; - 在所述转换器的输出处连接的低通滤波器（低通滤波器），用于接收所述信号 以模拟格式提供并提供所述重构的模拟信号作为输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。

公开(公告)号：US06940348B2

公开(公告)日：2005-09-06

申请号：US10471807

申请日：2002-07-05

申请人： Pierangelo Confalonieri ,  Germano Nicollini ,  Riccardo Martignone

发明人： Pierangelo Confalonieri ,  Germano Nicollini ,  Riccardo Martignone

IPC分类号： H03F1/30 ,  H03F3/45

CPC分类号： H03F3/45937 ,  H03F1/303

摘要： The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp−Vrefm)/2]*(C4−C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

摘要翻译： 该电路包括具有两个输入和两个输出的差分放大器和一个共模调节电路。 在放大器的调节端子和输出端之间，连接有第一和第二电容器以及通过受控开关分别与第一和第二电容器或第一和第二参考电压端子并联连接的第一和第二电容元件。 共模输出电压在设计开始时不是完全固定的，而是通过将适当的值归因于第一和第二电容元件来确定的; 更具体地说，它们的电容C3和C4以满足以下等式的方式选择：<？in-line-formula description =“In-line formula”end =“lead”？> Vcmn = Vrefl + [（Vrefp- Vrefm）/ 2] *（C 4 -C 3）/（C 3 + C 4），<？in-line-formula description =“In-line formula”end =“tail”？>其中Vcmn是所需的公共 模式输出电压，Vrefp和Vrefm是差分输出电压，Vrefl是第二参考端子的电压。

公开(公告)号：US06556072B1

公开(公告)日：2003-04-29

申请号：US08791281

申请日：1997-01-30

申请人： Germano Nicollini ,  Angelo Nagari

发明人： Germano Nicollini ,  Angelo Nagari

IPC分类号： H03K500

CPC分类号： G11C27/024 ,  G11C27/026 ,  H03F3/005 ,  H03H19/004 ,  H03K5/249

摘要： A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.

摘要翻译： 一种开关电容器电路，包括具有第一和第二输入端子的运算放大器和输出端子，所述第一输入端子连接到第一参考电位。 运算放大器设置有负反馈网络，其包括连接在运算放大器的第二输入端子和输出端子之间的第一电容元件，第二电容元件，其具有交替地连接到第二输入端子的第二输入端子 运算放大器和参考电位，以及连接到交替连接到运算放大器的信号输入端和所述第一输出端的第一电路节点的第二端。 电路还包括连接在电路节点和参考电位之间的第三电容元件。