公开(公告)号：US06704862B1

公开(公告)日：2004-03-09

申请号：US09591142

申请日：2000-06-09

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： One embodiment of the present invention provides a system that supports exception handling through use of a conditional trap instruction. The system supports a head thread that executes program instructions and a speculative thread that speculatively executes program instructions in advance of the head thread. During operation, the system uses the speculative thread to execute code, which includes an instruction that can cause an exception condition. After the instruction is executed, the system determines if the instruction caused the exception condition. If so, the system writes an exception condition indicator to a register. At some time in the future, the system executes a conditional trap instruction which examines a value in the register. If the value in the register is an exception condition indicator, the system executes a trap handling routine to handle the exception condition. Otherwise, the system proceeds with execution of the code. In one embodiment of the present invention, prior to executing the instruction, the system allows a compiler to optimize a program containing the instruction. This optimization process includes scheduling an exception testing instruction associated with the instruction to occupy a free instruction slot following the instruction. This exception testing instruction determines if the instruction causes the exception condition. In one embodiment of the present invention, the trap handling routine triggers a rollback operation to undo operations performed by the speculative thread.

摘要翻译： 本发明的一个实施例提供一种通过使用条件陷阱指令来支持异常处理的系统。 该系统支持执行程序指令的头线程和在头部线程之前推测性地执行程序指令的推测线程。 在运行期间，系统使用推测线程来执行代码，其中包含可能导致异常情况的指令。 执行指令后，系统确定指令是否引起异常情况。 如果是这样，系统会将一个异常状态指示器写入寄存器。 在将来的某个时间，系统执行条件陷阱指令，检查寄存器中的值。 如果寄存器中的值是异常条件指示符，系统将执行陷阱处理例程来处理异常情况。 否则，系统继续执行代码。 在本发明的一个实施例中，在执行指令之前，系统允许编译器优化包含该指令的程序。 该优化处理包括调度与指令相关联的异常测试指令，以占用指令之后的空闲指令槽。 该异常测试指令确定指令是否导致异常情况。 在本发明的一个实施例中，陷阱处理例程触发回滚操作以撤消由推测线程执行的操作。

公开(公告)号：US08447931B1

公开(公告)日：2013-05-21

申请号：US11173110

申请日：2005-07-01

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F12/00

CPC分类号： G06F9/30141 ,  G06F9/383 ,  G06F9/3867 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1075 ,  G11C8/08 ,  G11C2207/107 ,  G11C2207/108

摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

摘要翻译： 本发明的一个实施例提供一种支持多次执行的处理器。 该处理器包括一个寄存器文件，该寄存器文件包含一个存储单元阵列，其中存储单元包含处理器结构寄存器的位。 注册文件还包括多个读取端口和多个写入端口，以支持多次执行。 在操作期间，如果从给定寄存器同时读取多个读取端口，则寄存器文件被配置为：通过与该位相关联的单个位线，将给定寄存器的每个位从存储器单元阵列中读出; 并使用位于存储器单元阵列之外的驱动器将该位驱动到多个读取端口。 以这种方式，每个存储器单元仅在多端口读取操作期间仅驱动单个位线（而不是多个位线），从而允许存储器单元使用较小且更省电的驱动器进行读取操作。

公开(公告)号：US07930695B2

公开(公告)日：2011-04-19

申请号：US11418652

申请日：2006-05-05

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait. When the second thread reaches a second predetermined location in the multi-threaded program, the second thread signals the first thread by accessing the mailbox location, which causes the transactional execution of the first thread to fail, thereby causing the first thread to resume non-transactional execution from the location specified in the STE instruction. In this way, the second thread can signal to the first thread without the first thread having to poll a shared variable.

摘要翻译： 本发明的一个实施例提供了一种在多线程处理器上同步线程的系统。 系统通过使用第一个线程和第二个线程执行来自多线程程序的指令来启动。 当第一线程到达多线程程序中的预定位置时，第一线程执行开始 - 事务执行（STE）指令以开始事务执行，其中STE指令指定分支到事务执行失败的位置。 在随后的事务执行期间，第一个线程访问存储器中的邮箱位置（也可由第二个线程访问），然后执行使第一个线程等待的指令。 当第二线程到达多线程程序中的第二预定位置时，第二线程通过访问邮箱位置来发信号通知第一线程，这导致第一线程的事务性执行失败，从而使第一线程恢复为非线程， 从STE指令中指定的位置进行事务执行。 以这种方式，第二线程可以向第一线程发信号，而第一线程不必轮询共享变量。

公开(公告)号：US20100191993A1

公开(公告)日：2010-07-29

申请号：US12361422

申请日：2009-01-28

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

公开(公告)号：US20100049957A1

公开(公告)日：2010-02-25

申请号：US12197629

申请日：2008-08-25

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/30

CPC分类号： G06F9/3889 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

摘要翻译： 本发明的实施例提供一种在处理器中执行程序代码的系统。 系统通过使用主链在正常模式下执行程序代码，同时使用侦察模式中的从属线同时执行主链前面的程序代码来开始。 在使用下级线解析分支时，系统在推测分支分辨率表中记录分支的分辨率。 在随后使用主链遇到分支时，系统使用来自推测性分支分辨率表的记录分辨率来预测主股的分支的分辨率。 在确定分支的决议对于主要股份进行了错误估计时，系统确定下级股错误地预测了分行。 系统然后将下级线路恢复到分支，并重新启动执行程序代码的下级线程。

公开(公告)号：US07634641B2

公开(公告)日：2009-12-15

申请号：US11361257

申请日：2006-04-24

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/00 ,  G06F9/40

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode. During execution in the deferred mode, the second thread executes instructions deferred by the first thread.

摘要翻译： 本发明的一个实施例提供一种执行同时投机线程的系统。 系统通过使用第一个线程在正常执行模式下执行指令来启动。 在遇到数据相关的停顿条件时，第一个线程生成架构检查点，并以执行提前模式开始执行指令。 在执行提前模式期间，第一个线程执行可执行的指令，并将不能执行的指令拖到延迟队列中。 当数据相关的停顿条件已经解决时，第一个线程生成一个推测性检查点，并以执行提前模式继续执行。 同时，第二个线程以延迟模式开始执行。 在延迟模式执行期间，第二线程执行由第一线程延迟的指令。

公开(公告)号：US07574588B2

公开(公告)日：2009-08-11

申请号：US11359659

申请日：2006-02-21

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00

CPC分类号： G06F9/383 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/466 ,  G06F9/485

摘要： One embodiment of the present invention provides a system that facilitates interleaved execution of a head thread and a speculative thread within a single processor pipeline. The system operates by executing program instructions using the head thread, and by speculatively executing program instructions in advance of the head thread using the speculative thread, wherein the head thread and the speculative thread execute concurrently through time-multiplexed interleaving in the single processor pipeline.

摘要翻译： 本发明的一个实施例提供了一种促进在单个处理器流水线内的头部线程和推测线程的交错执行的系统。 该系统通过使用头部线程执行程序指令，并且通过使用推测性线程在头部线程之前推测性地执行程序指令来操作，其中头部线程和推测线程通过在单个处理器流水线中的时间多路复用交织同时执行。

公开(公告)号：US07565511B2

公开(公告)日：2009-07-21

申请号：US11425869

申请日：2006-06-22

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.

摘要翻译： 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。

公开(公告)号：US07509481B2

公开(公告)日：2009-03-24

申请号：US11277735

申请日：2006-03-28

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F9/00

CPC分类号： G06F9/30145 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3897

摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.

摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

公开(公告)号：US07490229B2

公开(公告)日：2009-02-10

申请号：US11093197

申请日：2005-03-29

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC分类号： G06F9/00

CPC分类号： G06F9/3844 ,  G06F9/30105 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

摘要翻译： 本发明的一个实施例提供一种便于在推测性执行期间存储可解析分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。 在操作期间，系统在处理器内执行代码。 在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。 在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。