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    Multi-state EEPROM having write-verify control circuit
    21.
    再颁专利
    Multi-state EEPROM having write-verify control circuit 有权

    公开(公告)号：USRE41021E1

    公开(公告)日：2009-12-01

    申请号：US11451588

    申请日：2006-06-13

    申请人： Tomoharu Tanaka ,  Gertjan Hemink

    发明人： Tomoharu Tanaka ,  Gertjan Hemink

    IPC分类号： G11C16/34

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

    Multi-state EEPROM having write-verify control circuit
    22.
    再颁专利
    Multi-state EEPROM having write-verify control circuit 有权

    公开(公告)号：USRE41019E1

    公开(公告)日：2009-12-01

    申请号：US11451589

    申请日：2006-06-13

    申请人： Tomoharu Tanaka ,  Gertjan Hemink

    发明人： Tomoharu Tanaka ,  Gertjan Hemink

    IPC分类号： G11C16/26

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

    Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell
    23.
    发明授权
    Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell 有权
    适用于将多值存储在单个存储单元中的非易失性半导体存储器件

    公开(公告)号：US07468908B2

    公开(公告)日：2008-12-23

    申请号：US11929152

    申请日：2007-10-30

    申请人： Tomoharu Tanaka

    发明人： Tomoharu Tanaka

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

    摘要： A non-volatile semiconductor memory device includes a non-volatile memory cell and a write circuit that is adapted to write data to the memory cell by supplying a write voltage and a write control voltage to the memory cell to change the write state of the memory cell, changing the supply of the write control voltage to reduce the rate of changing the write state, further changing the supply of the write control voltage to control the reduced rate of changing the write state and terminating the write operation to the memory cell while the rate of changing the write state is reduced.

    摘要翻译： 非易失性半导体存储器件包括非易失性存储器单元和写入电路，其适于通过向存储器单元提供写入电压和写入控制电压来将数据写入存储器单元，以改变存储器的写入状态 单元，改变写入控制电压的供应以减小改变写入状态的速率，进一步改变写入控制电压的供应以控制改变写入状态的降低速率并且终止对存储器单元的写入操作，同时 降低写入状态的速率。

    Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
    25.
    发明授权
    Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 有权
    具有与所选字线相邻的未选字线的非易失性半导体存储器件在不同的定时被充电用于程序干扰控制

    公开(公告)号：US07355887B2

    公开(公告)日：2008-04-08

    申请号：US11104599

    申请日：2005-04-13

    申请人： Hiroshi Nakamura ,  Tomoharu Tanaka

    发明人： Hiroshi Nakamura ,  Tomoharu Tanaka

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/30

    摘要： A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.

    摘要翻译： 非易失性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元 单元格阵列。 在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。 将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二 写入中间电压。

    Semiconductor memory device
    26.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07349259B2

    公开(公告)日：2008-03-25

    申请号：US11313826

    申请日：2005-12-22

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    Nonvolatile semiconductor memory device
    27.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07224612B2

    公开(公告)日：2007-05-29

    申请号：US11194799

    申请日：2005-08-02

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的多个存储单元。 对所有存储单元进行擦除操作。 然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并将11V施加到控制栅极 的剩余存储单元。 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Semiconductor memory device and electric device with the same
    28.
    发明授权
    Semiconductor memory device and electric device with the same 有权
    半导体存储器件和电器件相同

    公开(公告)号：US07164605B2

    公开(公告)日：2007-01-16

    申请号：US11305193

    申请日：2005-12-19

    申请人： Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

    发明人： Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

    IPC分类号： G11C16/06

    CPC分类号： G11C16/3468

    摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

    摘要翻译： 半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作， 同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到 芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取 执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。