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343 条记录 (耗时 0.027 秒)

    Charge pump redundancy in a memory
    1.
    发明授权
    Charge pump redundancy in a memory 有权
    存储器中的电荷泵冗余

    公开(公告)号：US09042180B2

    公开(公告)日：2015-05-26

    申请号：US13995166

    申请日：2012-03-25

    申请人： Toru Tanzawa ,  Tomoharu Tanaka

    发明人： Toru Tanzawa ,  Tomoharu Tanaka

    IPC分类号： G11C16/30 ,  G11C5/14 ,  G11C29/00

    CPC分类号： G06F1/32 ,  G11C5/145 ,  G11C16/30 ,  G11C29/702

    摘要： An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

    摘要翻译： 集成电路包括电路块，以利用来自电源输入和两个或更多个电荷泵阵列的负载电压的负载电流。 电荷泵阵列的输出耦合到电路块的功率输入。 集成电路包括一个或多个可修改的元件以禁用两个或更多个电荷泵阵列中的一个或多个。

    Architecture for 3-D NAND memory
    2.
    发明授权
    Architecture for 3-D NAND memory 有权
    3-D NAND存储器架构

    公开(公告)号：US08964474B2

    公开(公告)日：2015-02-24

    申请号：US13524872

    申请日：2012-06-15

    申请人： Midori Morooka ,  Tomoharu Tanaka

    发明人： Midori Morooka ,  Tomoharu Tanaka

    IPC分类号： G11C16/00

    CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/3427 ,  G11C2213/71

    摘要： Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

    摘要翻译： 描述了包括存储器单元串的堆叠阵列及其操作方法的装置。 装置包括减少几个常用部件的使用的结构，允许给定半导体区域的更大的器件密度和更小的器件尺寸。

    Memory segment accessing in a memory device
    3.
    发明授权
    Memory segment accessing in a memory device 有权
    内存段访问存储设备

    公开(公告)号：US08767470B2

    公开(公告)日：2014-07-01

    申请号：US13564883

    申请日：2012-08-02

    申请人： Tomoharu Tanaka

    发明人： Tomoharu Tanaka

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G06F12/0893 ,  G06F2212/2022 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2216/14

    摘要： Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.

    摘要翻译： 通过将所选择的存储器段和任何中间段的某些数据线耦合到相应的数据高速缓冲存储器，基本上同时读取存储器段的位线。 不用于将所选择的段耦合到数据高速缓存的未选择的存储器段的位线可以耦合到它们各自的源极线。

    MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE
    4.
    发明申请
    MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE 有权
    存储器件中的存储器部分访问

    公开(公告)号：US20120294088A1

    公开(公告)日：2012-11-22

    申请号：US13564883

    申请日：2012-08-02

    申请人： Tomoharu Tanaka

    发明人： Tomoharu Tanaka

    IPC分类号： G11C16/04

    CPC分类号： G06F12/0893 ,  G06F2212/2022 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2216/14

    摘要： Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.

    摘要翻译： 通过将所选择的存储器段和任何中间段的某些数据线耦合到相应的数据高速缓冲存储器，基本上同时读取存储器段的位线。 不用于将所选择的段耦合到数据高速缓存的未选择的存储器段的位线可以耦合到它们各自的源极线。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07952933B2

    公开(公告)日：2011-05-31

    申请号：US12632203

    申请日：2009-12-07

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL
    7.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL 有权
    非易失性半导体存储器件适用于存储单个存储器单元中的多值数据

    公开(公告)号：US20110090741A1

    公开(公告)日：2011-04-21

    申请号：US12967227

    申请日：2010-12-14

    申请人： Tomoharu Tanaka ,  Jian CHEN

    发明人： Tomoharu Tanaka ,  Jian CHEN

    IPC分类号： G11C16/10

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

    摘要翻译： 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

    Flash memory
    8.
    发明授权
    Flash memory 有权
    闪存

    公开(公告)号：US07908529B2

    公开(公告)日：2011-03-15

    申请号：US12371659

    申请日：2009-02-16

    申请人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

    发明人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

    IPC分类号： G11C29/00 ,  G11C16/04 ,  H03M13/00

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
    10.
    发明授权
    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell 有权
    适用于将多值数据存储在单个存储单元中的非易失性半导体存储器件

    公开(公告)号：US07864591B2

    公开(公告)日：2011-01-04

    申请号：US12652418

    申请日：2010-01-05

    申请人： Tomoharu Tanaka ,  Jian Chen

    发明人： Tomoharu Tanaka ,  Jian Chen

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

    摘要翻译： 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。